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98 lines
3.4 KiB
98 lines
3.4 KiB
/*
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* Copyright (C) 2014 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_DISASSEMBLER_DISASSEMBLER_ARM64_H_
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#define ART_DISASSEMBLER_DISASSEMBLER_ARM64_H_
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#include "disassembler.h"
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// TODO(VIXL): Make VIXL compile with -Wshadow.
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wshadow"
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#include "aarch64/decoder-aarch64.h"
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#include "aarch64/disasm-aarch64.h"
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#pragma GCC diagnostic pop
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namespace art {
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namespace arm64 {
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class CustomDisassembler final : public vixl::aarch64::Disassembler {
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public:
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explicit CustomDisassembler(DisassemblerOptions* options)
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: vixl::aarch64::Disassembler(),
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read_literals_(options->can_read_literals_),
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base_address_(options->base_address_),
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end_address_(options->end_address_),
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options_(options) {
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if (!options->absolute_addresses_) {
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MapCodeAddress(0,
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reinterpret_cast<const vixl::aarch64::Instruction*>(options->base_address_));
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}
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}
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// Use register aliases in the disassembly.
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void AppendRegisterNameToOutput(const vixl::aarch64::Instruction* instr,
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const vixl::aarch64::CPURegister& reg) override;
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// Improve the disassembly of literal load instructions.
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void VisitLoadLiteral(const vixl::aarch64::Instruction* instr) override;
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// Improve the disassembly of thread offset.
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void VisitLoadStoreUnsignedOffset(const vixl::aarch64::Instruction* instr) override;
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// Improve the disassembly of branch to thunk jumping to pointer from thread entrypoint.
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void VisitUnconditionalBranch(const vixl::aarch64::Instruction* instr) override;
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private:
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void AppendThreadOfsetName(const vixl::aarch64::Instruction* instr);
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// Indicate if the disassembler should read data loaded from literal pools.
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// This should only be enabled if reading the target of literal loads is safe.
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// Here are possible outputs when the option is on or off:
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// read_literals_ | disassembly
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// true | 0x72681558: 1c000acb ldr s11, pc+344 (addr 0x726816b0)
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// false | 0x72681558: 1c000acb ldr s11, pc+344 (addr 0x726816b0) (3.40282e+38)
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const bool read_literals_;
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// Valid address range: [base_address_, end_address_)
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const void* const base_address_;
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const void* const end_address_;
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DisassemblerOptions* options_;
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};
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class DisassemblerArm64 final : public Disassembler {
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public:
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explicit DisassemblerArm64(DisassemblerOptions* options) :
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Disassembler(options), disasm(options) {
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decoder.AppendVisitor(&disasm);
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}
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size_t Dump(std::ostream& os, const uint8_t* begin) override;
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void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) override;
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private:
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vixl::aarch64::Decoder decoder;
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CustomDisassembler disasm;
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DISALLOW_COPY_AND_ASSIGN(DisassemblerArm64);
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};
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} // namespace arm64
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} // namespace art
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#endif // ART_DISASSEMBLER_DISASSEMBLER_ARM64_H_
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