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779 lines
24 KiB
779 lines
24 KiB
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef __UAPI_MSMB_ISP__
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#define __UAPI_MSMB_ISP__
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#include <linux/videodev2.h>
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#include <media/msmb_camera.h>
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#define MAX_PLANES_PER_STREAM 3
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#define MAX_NUM_STREAM 7
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#define ISP_VERSION_48 48
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#define ISP_VERSION_47 47
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#define ISP_VERSION_46 46
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#define ISP_VERSION_44 44
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#define ISP_VERSION_40 40
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#define ISP_VERSION_32 32
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#define ISP_NATIVE_BUF_BIT (0x10000 << 0)
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#define ISP0_BIT (0x10000 << 1)
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#define ISP1_BIT (0x10000 << 2)
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#define ISP_META_CHANNEL_BIT (0x10000 << 3)
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#define ISP_SCRATCH_BUF_BIT (0x10000 << 4)
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#define ISP_OFFLINE_STATS_BIT (0x10000 << 5)
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#define ISP_SVHDR_IN_BIT (0x10000 << 6)
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#define ISP_SVHDR_OUT_BIT (0x10000 << 7)
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#define ISP_STATS_STREAM_BIT 0x80000000
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#define VFE_HW_LIMIT 1
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struct msm_vfe_cfg_cmd_list;
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enum ISP_START_PIXEL_PATTERN {
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ISP_BAYER_RGRGRG,
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ISP_BAYER_GRGRGR,
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ISP_BAYER_BGBGBG,
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ISP_BAYER_GBGBGB,
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ISP_YUV_YCbYCr,
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ISP_YUV_YCrYCb,
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ISP_YUV_CbYCrY,
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ISP_YUV_CrYCbY,
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ISP_PIX_PATTERN_MAX
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};
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enum msm_vfe_plane_fmt {
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Y_PLANE,
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CB_PLANE,
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CR_PLANE,
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CRCB_PLANE,
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CBCR_PLANE,
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VFE_PLANE_FMT_MAX
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};
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enum msm_vfe_input_src {
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VFE_PIX_0,
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VFE_RAW_0,
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VFE_RAW_1,
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VFE_RAW_2,
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VFE_SRC_MAX,
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};
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enum msm_vfe_axi_stream_src {
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PIX_ENCODER,
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PIX_VIEWFINDER,
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PIX_VIDEO,
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CAMIF_RAW,
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IDEAL_RAW,
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RDI_INTF_0,
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RDI_INTF_1,
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RDI_INTF_2,
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VFE_AXI_SRC_MAX
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};
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enum msm_vfe_frame_skip_pattern {
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NO_SKIP,
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EVERY_2FRAME,
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EVERY_3FRAME,
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EVERY_4FRAME,
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EVERY_5FRAME,
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EVERY_6FRAME,
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EVERY_7FRAME,
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EVERY_8FRAME,
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EVERY_16FRAME,
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EVERY_32FRAME,
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SKIP_ALL,
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SKIP_RANGE,
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MAX_SKIP,
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};
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#define MSM_VFE_STREAM_STOP_PERIOD 15
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enum msm_isp_stats_type {
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MSM_ISP_STATS_AEC,
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MSM_ISP_STATS_AF,
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MSM_ISP_STATS_AWB,
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MSM_ISP_STATS_RS,
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MSM_ISP_STATS_CS,
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MSM_ISP_STATS_IHIST,
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MSM_ISP_STATS_SKIN,
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MSM_ISP_STATS_BG,
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MSM_ISP_STATS_BF,
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MSM_ISP_STATS_BE,
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MSM_ISP_STATS_BHIST,
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MSM_ISP_STATS_BF_SCALE,
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MSM_ISP_STATS_HDR_BE,
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MSM_ISP_STATS_HDR_BHIST,
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MSM_ISP_STATS_AEC_BG,
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MSM_ISP_STATS_MAX
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};
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struct msm_isp_sw_framskip {
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uint32_t stats_type_mask;
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uint32_t stream_src_mask;
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enum msm_vfe_frame_skip_pattern skip_mode;
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uint32_t min_frame_id;
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uint32_t max_frame_id;
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};
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enum msm_vfe_testgen_color_pattern {
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COLOR_BAR_8_COLOR,
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UNICOLOR_WHITE,
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UNICOLOR_YELLOW,
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UNICOLOR_CYAN,
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UNICOLOR_GREEN,
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UNICOLOR_MAGENTA,
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UNICOLOR_RED,
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UNICOLOR_BLUE,
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UNICOLOR_BLACK,
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MAX_COLOR,
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};
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enum msm_vfe_camif_input {
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CAMIF_DISABLED,
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CAMIF_PAD_REG_INPUT,
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CAMIF_MIDDI_INPUT,
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CAMIF_MIPI_INPUT,
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};
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struct msm_vfe_fetch_engine_cfg {
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uint32_t input_format;
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uint32_t buf_width;
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uint32_t buf_height;
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uint32_t fetch_width;
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uint32_t fetch_height;
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uint32_t x_offset;
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uint32_t y_offset;
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uint32_t buf_stride;
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};
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enum msm_vfe_camif_output_format {
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CAMIF_QCOM_RAW,
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CAMIF_MIPI_RAW,
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CAMIF_PLAIN_8,
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CAMIF_PLAIN_16,
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CAMIF_MAX_FORMAT,
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};
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struct msm_vfe_camif_subsample_cfg {
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uint32_t irq_subsample_period;
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uint32_t irq_subsample_pattern;
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uint32_t sof_counter_step;
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uint32_t pixel_skip;
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uint32_t line_skip;
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uint32_t first_line;
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uint32_t last_line;
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uint32_t first_pixel;
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uint32_t last_pixel;
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enum msm_vfe_camif_output_format output_format;
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};
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struct msm_vfe_camif_cfg {
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uint32_t lines_per_frame;
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uint32_t pixels_per_line;
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uint32_t first_pixel;
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uint32_t last_pixel;
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uint32_t first_line;
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uint32_t last_line;
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uint32_t epoch_line0;
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uint32_t epoch_line1;
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uint32_t is_split;
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enum msm_vfe_camif_input camif_input;
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struct msm_vfe_camif_subsample_cfg subsample_cfg;
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};
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struct msm_vfe_testgen_cfg {
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uint32_t lines_per_frame;
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uint32_t pixels_per_line;
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uint32_t v_blank;
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uint32_t h_blank;
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enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern;
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uint32_t rotate_period;
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enum msm_vfe_testgen_color_pattern color_bar_pattern;
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uint32_t burst_num_frame;
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};
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enum msm_vfe_inputmux {
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CAMIF,
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TESTGEN,
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EXTERNAL_READ,
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};
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enum msm_vfe_stats_composite_group {
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STATS_COMPOSITE_GRP_NONE,
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STATS_COMPOSITE_GRP_1,
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STATS_COMPOSITE_GRP_2,
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STATS_COMPOSITE_GRP_MAX,
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};
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enum msm_vfe_hvx_streaming_cmd {
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HVX_DISABLE,
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HVX_ONE_WAY,
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HVX_ROUND_TRIP
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};
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struct msm_vfe_pix_cfg {
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struct msm_vfe_camif_cfg camif_cfg;
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struct msm_vfe_testgen_cfg testgen_cfg;
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struct msm_vfe_fetch_engine_cfg fetch_engine_cfg;
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enum msm_vfe_inputmux input_mux;
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enum ISP_START_PIXEL_PATTERN pixel_pattern;
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uint32_t input_format;
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enum msm_vfe_hvx_streaming_cmd hvx_cmd;
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uint32_t is_split;
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};
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struct msm_vfe_rdi_cfg {
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uint8_t cid;
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uint8_t frame_based;
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};
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struct msm_vfe_input_cfg {
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union {
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struct msm_vfe_pix_cfg pix_cfg;
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struct msm_vfe_rdi_cfg rdi_cfg;
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} d;
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enum msm_vfe_input_src input_src;
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uint32_t input_pix_clk;
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};
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struct msm_vfe_fetch_eng_start {
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uint32_t session_id;
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uint32_t stream_id;
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uint32_t buf_idx;
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uint8_t offline_mode;
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uint32_t fd;
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uint32_t buf_addr;
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uint32_t frame_id;
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};
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enum msm_vfe_fetch_eng_pass {
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OFFLINE_FIRST_PASS,
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OFFLINE_SECOND_PASS,
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OFFLINE_MAX_PASS,
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};
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struct msm_vfe_fetch_eng_multi_pass_start {
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uint32_t session_id;
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uint32_t stream_id;
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uint32_t buf_idx;
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uint8_t offline_mode;
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uint32_t fd;
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uint32_t buf_addr;
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uint32_t frame_id;
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uint32_t output_buf_idx;
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uint32_t input_buf_offset;
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enum msm_vfe_fetch_eng_pass offline_pass;
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uint32_t output_stream_id;
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};
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struct msm_vfe_axi_plane_cfg {
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uint32_t output_width;
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uint32_t output_height;
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uint32_t output_stride;
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uint32_t output_scan_lines;
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uint32_t output_plane_format;
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uint32_t plane_addr_offset;
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uint8_t csid_src;
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uint8_t rdi_cid;
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};
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enum msm_stream_rdi_input_type {
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MSM_CAMERA_RDI_MIN,
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MSM_CAMERA_RDI_PDAF,
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MSM_CAMERA_RDI_MAX,
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};
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struct msm_vfe_axi_stream_request_cmd {
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uint32_t session_id;
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uint32_t stream_id;
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uint32_t vt_enable;
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uint32_t output_format;
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enum msm_vfe_axi_stream_src stream_src;
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struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
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uint32_t burst_count;
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uint32_t hfr_mode;
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uint8_t frame_base;
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uint32_t init_frame_drop;
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enum msm_vfe_frame_skip_pattern frame_skip_pattern;
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uint8_t buf_divert;
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uint32_t axi_stream_handle;
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uint32_t controllable_output;
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uint32_t burst_len;
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enum msm_stream_rdi_input_type rdi_input_type;
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};
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struct msm_vfe_axi_stream_release_cmd {
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uint32_t stream_handle;
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};
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enum msm_vfe_axi_stream_cmd {
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STOP_STREAM,
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START_STREAM,
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STOP_IMMEDIATELY,
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};
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struct msm_vfe_axi_stream_cfg_cmd {
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uint8_t num_streams;
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uint32_t stream_handle[VFE_AXI_SRC_MAX];
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enum msm_vfe_axi_stream_cmd cmd;
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uint8_t sync_frame_id_src;
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};
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enum msm_vfe_axi_stream_update_type {
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ENABLE_STREAM_BUF_DIVERT,
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DISABLE_STREAM_BUF_DIVERT,
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UPDATE_STREAM_FRAMEDROP_PATTERN,
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UPDATE_STREAM_STATS_FRAMEDROP_PATTERN,
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UPDATE_STREAM_AXI_CONFIG,
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UPDATE_STREAM_REQUEST_FRAMES,
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UPDATE_STREAM_ADD_BUFQ,
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UPDATE_STREAM_REMOVE_BUFQ,
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UPDATE_STREAM_SW_FRAME_DROP,
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UPDATE_STREAM_REQUEST_FRAMES_VER2,
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UPDATE_STREAM_OFFLINE_AXI_CONFIG,
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};
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#define UPDATE_STREAM_REQUEST_FRAMES_VER2 UPDATE_STREAM_REQUEST_FRAMES_VER2
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enum msm_vfe_iommu_type {
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IOMMU_ATTACH,
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IOMMU_DETACH,
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};
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enum msm_vfe_buff_queue_id {
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VFE_BUF_QUEUE_DEFAULT,
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VFE_BUF_QUEUE_SHARED,
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VFE_BUF_QUEUE_MAX,
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};
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struct msm_vfe_axi_stream_cfg_update_info {
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uint32_t stream_handle;
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uint32_t output_format;
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uint32_t user_stream_id;
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uint32_t frame_id;
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enum msm_vfe_frame_skip_pattern skip_pattern;
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struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
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struct msm_isp_sw_framskip sw_skip_info;
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};
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struct msm_vfe_axi_stream_cfg_update_info_req_frm {
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uint32_t stream_handle;
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uint32_t user_stream_id;
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uint32_t frame_id;
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uint32_t buf_index;
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};
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struct msm_vfe_axi_halt_cmd {
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uint32_t stop_camif;
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uint32_t overflow_detected;
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uint32_t blocking_halt;
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};
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struct msm_vfe_axi_reset_cmd {
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uint32_t blocking;
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uint32_t frame_id;
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};
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struct msm_vfe_axi_restart_cmd {
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uint32_t enable_camif;
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};
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struct msm_vfe_axi_stream_update_cmd {
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uint32_t num_streams;
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enum msm_vfe_axi_stream_update_type update_type;
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union {
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struct msm_vfe_axi_stream_cfg_update_info update_info[MSM_ISP_STATS_MAX];
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struct msm_vfe_axi_stream_cfg_update_info_req_frm req_frm_ver2;
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};
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};
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struct msm_vfe_smmu_attach_cmd {
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uint32_t security_mode;
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uint32_t iommu_attach_mode;
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};
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struct msm_vfe_stats_stream_request_cmd {
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uint32_t session_id;
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uint32_t stream_id;
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enum msm_isp_stats_type stats_type;
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uint32_t composite_flag;
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uint32_t framedrop_pattern;
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uint32_t init_frame_drop;
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uint32_t irq_subsample_pattern;
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uint32_t buffer_offset;
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uint32_t stream_handle;
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};
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struct msm_vfe_stats_stream_release_cmd {
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uint32_t stream_handle;
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};
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struct msm_vfe_stats_stream_cfg_cmd {
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uint8_t num_streams;
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uint32_t stream_handle[MSM_ISP_STATS_MAX];
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uint8_t enable;
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uint32_t stats_burst_len;
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};
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enum msm_vfe_reg_cfg_type {
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VFE_WRITE,
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VFE_WRITE_MB,
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VFE_READ,
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VFE_CFG_MASK,
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VFE_WRITE_DMI_16BIT,
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VFE_WRITE_DMI_32BIT,
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VFE_WRITE_DMI_64BIT,
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VFE_READ_DMI_16BIT,
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VFE_READ_DMI_32BIT,
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VFE_READ_DMI_64BIT,
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GET_MAX_CLK_RATE,
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GET_CLK_RATES,
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GET_ISP_ID,
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VFE_HW_UPDATE_LOCK,
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VFE_HW_UPDATE_UNLOCK,
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SET_WM_UB_SIZE,
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SET_UB_POLICY,
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GET_VFE_HW_LIMIT,
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};
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struct msm_vfe_cfg_cmd2 {
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uint16_t num_cfg;
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uint16_t cmd_len;
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void * cfg_data;
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void * cfg_cmd;
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};
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struct msm_vfe_cfg_cmd_list {
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struct msm_vfe_cfg_cmd2 cfg_cmd;
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struct msm_vfe_cfg_cmd_list * next;
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uint32_t next_size;
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};
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struct msm_vfe_reg_rw_info {
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uint32_t reg_offset;
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uint32_t cmd_data_offset;
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uint32_t len;
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};
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struct msm_vfe_reg_mask_info {
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uint32_t reg_offset;
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uint32_t mask;
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uint32_t val;
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};
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struct msm_vfe_reg_dmi_info {
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uint32_t hi_tbl_offset;
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uint32_t lo_tbl_offset;
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uint32_t len;
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};
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struct msm_vfe_reg_cfg_cmd {
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union {
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struct msm_vfe_reg_rw_info rw_info;
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struct msm_vfe_reg_mask_info mask_info;
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struct msm_vfe_reg_dmi_info dmi_info;
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} u;
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enum msm_vfe_reg_cfg_type cmd_type;
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};
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enum vfe_sd_type {
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VFE_SD_0 = 0,
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VFE_SD_1,
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VFE_SD_COMMON,
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VFE_SD_MAX,
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};
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#define MS_NUM_SLAVE_MAX 1
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enum msm_vfe_dual_hw_type {
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DUAL_NONE = 0,
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DUAL_HW_VFE_SPLIT = 1,
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DUAL_HW_MASTER_SLAVE = 2,
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};
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enum msm_vfe_dual_hw_ms_type {
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MS_TYPE_NONE,
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MS_TYPE_MASTER,
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MS_TYPE_SLAVE,
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};
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struct msm_isp_set_dual_hw_ms_cmd {
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uint8_t num_src;
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enum msm_vfe_dual_hw_ms_type dual_hw_ms_type;
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enum msm_vfe_input_src primary_intf;
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enum msm_vfe_input_src input_src[VFE_SRC_MAX];
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uint32_t sof_delta_threshold;
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};
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enum msm_isp_buf_type {
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ISP_PRIVATE_BUF,
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ISP_SHARE_BUF,
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MAX_ISP_BUF_TYPE,
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};
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struct msm_isp_unmap_buf_req {
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uint32_t fd;
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};
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struct msm_isp_buf_request {
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uint32_t session_id;
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uint32_t stream_id;
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uint8_t num_buf;
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uint32_t handle;
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|
enum msm_isp_buf_type buf_type;
|
|
};
|
|
struct msm_isp_buf_request_ver2 {
|
|
uint32_t session_id;
|
|
uint32_t stream_id;
|
|
uint8_t num_buf;
|
|
uint32_t handle;
|
|
enum msm_isp_buf_type buf_type;
|
|
enum smmu_attach_mode security_mode;
|
|
uint32_t reserved[4];
|
|
};
|
|
struct msm_isp_qbuf_plane {
|
|
uint32_t addr;
|
|
uint32_t offset;
|
|
uint32_t length;
|
|
};
|
|
struct msm_isp_qbuf_buffer {
|
|
struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM];
|
|
uint32_t num_planes;
|
|
};
|
|
struct msm_isp_qbuf_info {
|
|
uint32_t handle;
|
|
int32_t buf_idx;
|
|
struct msm_isp_qbuf_buffer buffer;
|
|
uint32_t dirty_buf;
|
|
};
|
|
struct msm_isp_clk_rates {
|
|
uint32_t svs_rate;
|
|
uint32_t nominal_rate;
|
|
uint32_t high_rate;
|
|
};
|
|
struct msm_vfe_axi_src_state {
|
|
enum msm_vfe_input_src input_src;
|
|
uint32_t src_active;
|
|
uint32_t src_frame_id;
|
|
};
|
|
enum msm_isp_event_mask_index {
|
|
ISP_EVENT_MASK_INDEX_STATS_NOTIFY = 0,
|
|
ISP_EVENT_MASK_INDEX_ERROR = 1,
|
|
ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT = 2,
|
|
ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE = 3,
|
|
ISP_EVENT_MASK_INDEX_REG_UPDATE = 4,
|
|
ISP_EVENT_MASK_INDEX_SOF = 5,
|
|
ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6,
|
|
ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7,
|
|
ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8,
|
|
ISP_EVENT_MASK_INDEX_BUF_DONE = 9,
|
|
ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING = 10,
|
|
ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH = 11,
|
|
ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR = 12,
|
|
};
|
|
#define ISP_EVENT_SUBS_MASK_NONE 0
|
|
#define ISP_EVENT_SUBS_MASK_STATS_NOTIFY (1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY)
|
|
#define ISP_EVENT_SUBS_MASK_ERROR (1 << ISP_EVENT_MASK_INDEX_ERROR)
|
|
#define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT (1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT)
|
|
#define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE (1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE)
|
|
#define ISP_EVENT_SUBS_MASK_REG_UPDATE (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE)
|
|
#define ISP_EVENT_SUBS_MASK_SOF (1 << ISP_EVENT_MASK_INDEX_SOF)
|
|
#define ISP_EVENT_SUBS_MASK_BUF_DIVERT (1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT)
|
|
#define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY (1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY)
|
|
#define ISP_EVENT_SUBS_MASK_FE_READ_DONE (1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE)
|
|
#define ISP_EVENT_SUBS_MASK_BUF_DONE (1 << ISP_EVENT_MASK_INDEX_BUF_DONE)
|
|
#define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING)
|
|
#define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH (1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH)
|
|
#define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR (1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR)
|
|
enum msm_isp_event_idx {
|
|
ISP_REG_UPDATE = 0,
|
|
ISP_EPOCH_0 = 1,
|
|
ISP_EPOCH_1 = 2,
|
|
ISP_START_ACK = 3,
|
|
ISP_STOP_ACK = 4,
|
|
ISP_IRQ_VIOLATION = 5,
|
|
ISP_STATS_OVERFLOW = 6,
|
|
ISP_BUF_DONE = 7,
|
|
ISP_FE_RD_DONE = 8,
|
|
ISP_IOMMU_P_FAULT = 9,
|
|
ISP_ERROR = 10,
|
|
ISP_HW_FATAL_ERROR = 11,
|
|
ISP_PING_PONG_MISMATCH = 12,
|
|
ISP_REG_UPDATE_MISSING = 13,
|
|
ISP_BUF_FATAL_ERROR = 14,
|
|
ISP_EVENT_MAX = 15
|
|
};
|
|
#define ISP_EVENT_OFFSET 8
|
|
#define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START)
|
|
#define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET))
|
|
#define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET))
|
|
#define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET))
|
|
#define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET))
|
|
#define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE)
|
|
#define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0)
|
|
#define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1)
|
|
#define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK)
|
|
#define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK)
|
|
#define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION)
|
|
#define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW)
|
|
#define ISP_EVENT_ERROR (ISP_EVENT_BASE + ISP_ERROR)
|
|
#define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE)
|
|
#define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1)
|
|
#define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE)
|
|
#define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE)
|
|
#define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE)
|
|
#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX)
|
|
#define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE)
|
|
#define ISP_EVENT_IOMMU_P_FAULT (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT)
|
|
#define ISP_EVENT_HW_FATAL_ERROR (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR)
|
|
#define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH)
|
|
#define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING)
|
|
#define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR)
|
|
#define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE)
|
|
struct msm_isp_buf_event {
|
|
uint32_t session_id;
|
|
uint32_t stream_id;
|
|
uint32_t handle;
|
|
uint32_t output_format;
|
|
int8_t buf_idx;
|
|
};
|
|
struct msm_isp_fetch_eng_event {
|
|
uint32_t session_id;
|
|
uint32_t stream_id;
|
|
uint32_t handle;
|
|
uint32_t fd;
|
|
int8_t buf_idx;
|
|
int8_t offline_mode;
|
|
};
|
|
struct msm_isp_stats_event {
|
|
uint32_t stats_mask;
|
|
uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX];
|
|
uint8_t pd_stats_idx;
|
|
};
|
|
struct msm_isp_stream_ack {
|
|
uint32_t session_id;
|
|
uint32_t stream_id;
|
|
uint32_t handle;
|
|
};
|
|
enum msm_vfe_error_type {
|
|
ISP_ERROR_NONE,
|
|
ISP_ERROR_CAMIF,
|
|
ISP_ERROR_BUS_OVERFLOW,
|
|
ISP_ERROR_RETURN_EMPTY_BUFFER,
|
|
ISP_ERROR_FRAME_ID_MISMATCH,
|
|
ISP_ERROR_MAX,
|
|
};
|
|
struct msm_isp_error_info {
|
|
enum msm_vfe_error_type err_type;
|
|
uint32_t session_id;
|
|
uint32_t stream_id;
|
|
uint32_t stream_id_mask;
|
|
};
|
|
struct msm_isp_ms_delta_info {
|
|
uint8_t num_delta_info;
|
|
uint32_t delta[MS_NUM_SLAVE_MAX];
|
|
};
|
|
struct msm_isp_output_info {
|
|
uint8_t regs_not_updated;
|
|
uint16_t output_err_mask;
|
|
uint8_t stream_framedrop_mask;
|
|
uint16_t stats_framedrop_mask;
|
|
};
|
|
struct msm_isp_sof_info {
|
|
uint8_t regs_not_updated;
|
|
uint16_t reg_update_fail_mask;
|
|
uint32_t stream_get_buf_fail_mask;
|
|
uint16_t stats_get_buf_fail_mask;
|
|
struct msm_isp_ms_delta_info ms_delta_info;
|
|
uint16_t axi_updating_mask;
|
|
uint32_t reg_update_fail_mask_ext;
|
|
};
|
|
#define AXI_UPDATING_MASK 1
|
|
#define REG_UPDATE_FAIL_MASK_EXT 1
|
|
struct msm_isp_event_data {
|
|
struct timeval timestamp;
|
|
struct timeval mono_timestamp;
|
|
uint32_t frame_id;
|
|
union {
|
|
struct msm_isp_stats_event stats;
|
|
struct msm_isp_buf_event buf_done;
|
|
struct msm_isp_fetch_eng_event fetch_done;
|
|
struct msm_isp_error_info error_info;
|
|
struct msm_isp_output_info output_info;
|
|
struct msm_isp_sof_info sof_info;
|
|
} u;
|
|
};
|
|
enum msm_vfe_ahb_clk_vote {
|
|
MSM_ISP_CAMERA_AHB_SVS_VOTE = 1,
|
|
MSM_ISP_CAMERA_AHB_TURBO_VOTE = 2,
|
|
MSM_ISP_CAMERA_AHB_NOMINAL_VOTE = 3,
|
|
MSM_ISP_CAMERA_AHB_SUSPEND_VOTE = 4,
|
|
};
|
|
struct msm_isp_ahb_clk_cfg {
|
|
uint32_t vote;
|
|
uint32_t reserved[2];
|
|
};
|
|
enum msm_vfe_dual_cam_sync_mode {
|
|
MSM_ISP_DUAL_CAM_ASYNC,
|
|
MSM_ISP_DUAL_CAM_SYNC,
|
|
};
|
|
struct msm_isp_dual_hw_master_slave_sync {
|
|
uint32_t sync_mode;
|
|
uint32_t reserved[2];
|
|
};
|
|
struct msm_vfe_dual_lpm_mode {
|
|
enum msm_vfe_axi_stream_src stream_src[VFE_AXI_SRC_MAX];
|
|
uint32_t num_src;
|
|
uint32_t lpm_mode;
|
|
};
|
|
#define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8')
|
|
#define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8')
|
|
#define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8')
|
|
#define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8')
|
|
#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0')
|
|
#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0')
|
|
#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0')
|
|
#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0')
|
|
#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2')
|
|
#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2')
|
|
#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2')
|
|
#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2')
|
|
#define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4')
|
|
#define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4')
|
|
#define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4')
|
|
#define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4')
|
|
#define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0')
|
|
#define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0')
|
|
#define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0')
|
|
#define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0')
|
|
#define V4L2_PIX_FMT_P16BGGR12 v4l2_fourcc('P', 'B', 'G', '2')
|
|
#define V4L2_PIX_FMT_P16GBRG12 v4l2_fourcc('P', 'G', 'B', '2')
|
|
#define V4L2_PIX_FMT_P16GRBG12 v4l2_fourcc('P', 'G', 'R', '2')
|
|
#define V4L2_PIX_FMT_P16RGGB12 v4l2_fourcc('P', 'R', 'G', '2')
|
|
#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4')
|
|
#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1')
|
|
#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T')
|
|
#define V4L2_PIX_FMT_META10 v4l2_fourcc('Q', 'M', '1', '0')
|
|
#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4')
|
|
#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4')
|
|
#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4')
|
|
#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4')
|
|
enum msm_isp_ioctl_cmd_code {
|
|
MSM_VFE_REG_CFG = BASE_VIDIOC_PRIVATE,
|
|
MSM_ISP_REQUEST_BUF,
|
|
MSM_ISP_ENQUEUE_BUF,
|
|
MSM_ISP_RELEASE_BUF,
|
|
MSM_ISP_REQUEST_STREAM,
|
|
MSM_ISP_CFG_STREAM,
|
|
MSM_ISP_RELEASE_STREAM,
|
|
MSM_ISP_INPUT_CFG,
|
|
MSM_ISP_SET_SRC_STATE,
|
|
MSM_ISP_REQUEST_STATS_STREAM,
|
|
MSM_ISP_CFG_STATS_STREAM,
|
|
MSM_ISP_RELEASE_STATS_STREAM,
|
|
MSM_ISP_REG_UPDATE_CMD,
|
|
MSM_ISP_UPDATE_STREAM,
|
|
MSM_VFE_REG_LIST_CFG,
|
|
MSM_ISP_SMMU_ATTACH,
|
|
MSM_ISP_UPDATE_STATS_STREAM,
|
|
MSM_ISP_AXI_HALT,
|
|
MSM_ISP_AXI_RESET,
|
|
MSM_ISP_AXI_RESTART,
|
|
MSM_ISP_FETCH_ENG_START,
|
|
MSM_ISP_DEQUEUE_BUF,
|
|
MSM_ISP_SET_DUAL_HW_MASTER_SLAVE,
|
|
MSM_ISP_MAP_BUF_START_FE,
|
|
MSM_ISP_UNMAP_BUF,
|
|
MSM_ISP_AHB_CLK_CFG,
|
|
MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC,
|
|
MSM_ISP_FETCH_ENG_MULTI_PASS_START,
|
|
MSM_ISP_MAP_BUF_START_MULTI_PASS_FE,
|
|
MSM_ISP_REQUEST_BUF_VER2,
|
|
MSM_ISP_DUAL_HW_LPM_MODE,
|
|
};
|
|
#define VIDIOC_MSM_VFE_REG_CFG _IOWR('V', MSM_VFE_REG_CFG, struct msm_vfe_cfg_cmd2)
|
|
#define VIDIOC_MSM_ISP_REQUEST_BUF _IOWR('V', MSM_ISP_REQUEST_BUF, struct msm_isp_buf_request)
|
|
#define VIDIOC_MSM_ISP_ENQUEUE_BUF _IOWR('V', MSM_ISP_ENQUEUE_BUF, struct msm_isp_qbuf_info)
|
|
#define VIDIOC_MSM_ISP_RELEASE_BUF _IOWR('V', MSM_ISP_RELEASE_BUF, struct msm_isp_buf_request)
|
|
#define VIDIOC_MSM_ISP_REQUEST_STREAM _IOWR('V', MSM_ISP_REQUEST_STREAM, struct msm_vfe_axi_stream_request_cmd)
|
|
#define VIDIOC_MSM_ISP_CFG_STREAM _IOWR('V', MSM_ISP_CFG_STREAM, struct msm_vfe_axi_stream_cfg_cmd)
|
|
#define VIDIOC_MSM_ISP_RELEASE_STREAM _IOWR('V', MSM_ISP_RELEASE_STREAM, struct msm_vfe_axi_stream_release_cmd)
|
|
#define VIDIOC_MSM_ISP_INPUT_CFG _IOWR('V', MSM_ISP_INPUT_CFG, struct msm_vfe_input_cfg)
|
|
#define VIDIOC_MSM_ISP_SET_SRC_STATE _IOWR('V', MSM_ISP_SET_SRC_STATE, struct msm_vfe_axi_src_state)
|
|
#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM _IOWR('V', MSM_ISP_REQUEST_STATS_STREAM, struct msm_vfe_stats_stream_request_cmd)
|
|
#define VIDIOC_MSM_ISP_CFG_STATS_STREAM _IOWR('V', MSM_ISP_CFG_STATS_STREAM, struct msm_vfe_stats_stream_cfg_cmd)
|
|
#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM _IOWR('V', MSM_ISP_RELEASE_STATS_STREAM, struct msm_vfe_stats_stream_release_cmd)
|
|
#define VIDIOC_MSM_ISP_REG_UPDATE_CMD _IOWR('V', MSM_ISP_REG_UPDATE_CMD, enum msm_vfe_input_src)
|
|
#define VIDIOC_MSM_ISP_UPDATE_STREAM _IOWR('V', MSM_ISP_UPDATE_STREAM, struct msm_vfe_axi_stream_update_cmd)
|
|
#define VIDIOC_MSM_VFE_REG_LIST_CFG _IOWR('V', MSM_VFE_REG_LIST_CFG, struct msm_vfe_cfg_cmd_list)
|
|
#define VIDIOC_MSM_ISP_SMMU_ATTACH _IOWR('V', MSM_ISP_SMMU_ATTACH, struct msm_vfe_smmu_attach_cmd)
|
|
#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM _IOWR('V', MSM_ISP_UPDATE_STATS_STREAM, struct msm_vfe_axi_stream_update_cmd)
|
|
#define VIDIOC_MSM_ISP_AXI_HALT _IOWR('V', MSM_ISP_AXI_HALT, struct msm_vfe_axi_halt_cmd)
|
|
#define VIDIOC_MSM_ISP_AXI_RESET _IOWR('V', MSM_ISP_AXI_RESET, struct msm_vfe_axi_reset_cmd)
|
|
#define VIDIOC_MSM_ISP_AXI_RESTART _IOWR('V', MSM_ISP_AXI_RESTART, struct msm_vfe_axi_restart_cmd)
|
|
#define VIDIOC_MSM_ISP_FETCH_ENG_START _IOWR('V', MSM_ISP_FETCH_ENG_START, struct msm_vfe_fetch_eng_start)
|
|
#define VIDIOC_MSM_ISP_DEQUEUE_BUF _IOWR('V', MSM_ISP_DEQUEUE_BUF, struct msm_isp_qbuf_info)
|
|
#define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE _IOWR('V', MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, struct msm_isp_set_dual_hw_ms_cmd)
|
|
#define VIDIOC_MSM_ISP_MAP_BUF_START_FE _IOWR('V', MSM_ISP_MAP_BUF_START_FE, struct msm_vfe_fetch_eng_start)
|
|
#define VIDIOC_MSM_ISP_UNMAP_BUF _IOWR('V', MSM_ISP_UNMAP_BUF, struct msm_isp_unmap_buf_req)
|
|
#define VIDIOC_MSM_ISP_AHB_CLK_CFG _IOWR('V', MSM_ISP_AHB_CLK_CFG, struct msm_isp_ahb_clk_cfg)
|
|
#define VIDIOC_MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC _IOWR('V', MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, struct msm_isp_dual_hw_master_slave_sync)
|
|
#define VIDIOC_MSM_ISP_FETCH_ENG_MULTI_PASS_START _IOWR('V', MSM_ISP_FETCH_ENG_MULTI_PASS_START, struct msm_vfe_fetch_eng_multi_pass_start)
|
|
#define VIDIOC_MSM_ISP_MAP_BUF_START_MULTI_PASS_FE _IOWR('V', MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, struct msm_vfe_fetch_eng_multi_pass_start)
|
|
#define VIDIOC_MSM_ISP_REQUEST_BUF_VER2 _IOWR('V', MSM_ISP_REQUEST_BUF_VER2, struct msm_isp_buf_request_ver2)
|
|
#define VIDIOC_MSM_ISP_DUAL_HW_LPM_MODE _IOWR('V', MSM_ISP_DUAL_HW_LPM_MODE, struct msm_vfe_dual_lpm_mode)
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#endif
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