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101 lines
3.8 KiB
101 lines
3.8 KiB
/*
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Copyright (c) 2009, 2010, 2011, 2013 STMicroelectronics
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Written by Christophe Lyon
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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#if defined(__arm__) || defined(__aarch64__)
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#include <arm_neon.h>
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#else
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#include "stm-arm-neon.h"
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#endif
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#include "stm-arm-neon-ref.h"
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#define TEST_MSG "VCOMBINE"
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void exec_vcombine (void)
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{
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/* Basic test: vec128=vcombine(vec64_a, vec64_b), then store the result. */
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#define TEST_VCOMBINE(T1, T2, W, N, N2) \
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VECT_VAR(vector128, T1, W, N2) = \
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vcombine_##T2##W(VECT_VAR(vector64_a, T1, W, N), \
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VECT_VAR(vector64_b, T1, W, N)); \
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vst1q_##T2##W(VECT_VAR(result, T1, W, N2), VECT_VAR(vector128, T1, W, N2))
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/* With ARM RVCT, we need to declare variables before any executable
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statement */
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DECL_VARIABLE_64BITS_VARIANTS(vector64_a);
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DECL_VARIABLE_64BITS_VARIANTS(vector64_b);
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DECL_VARIABLE_128BITS_VARIANTS(vector128);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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DECL_VARIABLE(vector64_a, float, 16, 4);
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DECL_VARIABLE(vector64_b, float, 16, 4);
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DECL_VARIABLE(vector64_b_init, uint, 16, 4);
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DECL_VARIABLE(vector128, float, 16, 8);
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#endif
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TEST_MACRO_64BITS_VARIANTS_2_5(VLOAD, vector64_a, buffer);
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VLOAD(vector64_a, buffer, , float, f, 32, 2);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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VLOAD(vector64_a, buffer, , float, f, 16, 4);
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#endif
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VDUP(vector64_b, , int, s, 8, 8, 0x11);
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VDUP(vector64_b, , int, s, 16, 4, 0x22);
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VDUP(vector64_b, , int, s, 32, 2, 0x33);
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VDUP(vector64_b, , int, s, 64, 1, 0x44);
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VDUP(vector64_b, , uint, u, 8, 8, 0x55);
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VDUP(vector64_b, , uint, u, 16, 4, 0x66);
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VDUP(vector64_b, , uint, u, 32, 2, 0x77);
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VDUP(vector64_b, , uint, u, 64, 1, 0x88);
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VDUP(vector64_b, , poly, p, 8, 8, 0x55);
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VDUP(vector64_b, , poly, p, 16, 4, 0x66);
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VDUP(vector64_b, , float, f, 32, 2, 3.3f);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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/* There is no vdup_n_f16, so we need another initialization
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method. */
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VDUP(vector64_b_init, , uint, u, 16, 4, 0x4b80 /* 15 */);
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VECT_VAR(vector64_b, float, 16, 4) =
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vreinterpret_f16_u16(VECT_VAR(vector64_b_init, uint, 16, 4));
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#endif
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clean_results ();
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TEST_VCOMBINE(int, s, 8, 8, 16);
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TEST_VCOMBINE(int, s, 16, 4, 8);
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TEST_VCOMBINE(int, s, 32, 2, 4);
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TEST_VCOMBINE(int, s, 64, 1, 2);
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TEST_VCOMBINE(uint, u, 8, 8, 16);
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TEST_VCOMBINE(uint, u, 16, 4, 8);
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TEST_VCOMBINE(uint, u, 32, 2, 4);
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TEST_VCOMBINE(uint, u, 64, 1, 2);
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TEST_VCOMBINE(poly, p, 8, 8, 16);
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TEST_VCOMBINE(poly, p, 16, 4, 8);
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TEST_VCOMBINE(float, f, 32, 2, 4);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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TEST_VCOMBINE(float, f, 16, 4, 8);
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#endif
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dump_results_hex (TEST_MSG);
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}
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