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237 lines
9.0 KiB
237 lines
9.0 KiB
/*
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Copyright (c) 2009, 2010, 2011, 2013 STMicroelectronics
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Written by Christophe Lyon
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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#if defined(__arm__) || defined(__aarch64__)
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#include <arm_neon.h>
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#else
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#include "stm-arm-neon.h"
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#endif
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#include "stm-arm-neon-ref.h"
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#include <math.h>
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#define TEST_MSG "VCVT/VCVTQ"
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void exec_vcvt (void)
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{
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int i;
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/* Basic test: y=vcvt(x), then store the result. */
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#define TEST_VCVT(Q, T1, T2, W, N, TS1, TS2) \
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VECT_VAR(vector_res, T1, W, N) = \
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vcvt##Q##_##T2##W##_##TS2##W(VECT_VAR(vector, TS1, W, N)); \
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vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
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VECT_VAR(vector_res, T1, W, N)); \
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DUMP(TEST_MSG, T1, W, N, PRIx##W);
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#define TEST_VCVT_FP(Q, T1, T2, W, N, TS1, TS2) \
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VECT_VAR(vector_res, T1, W, N) = \
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vcvt##Q##_##T2##W##_##TS2##W(VECT_VAR(vector, TS1, W, N)); \
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vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
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VECT_VAR(vector_res, T1, W, N)); \
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DUMP_FP(TEST_MSG, T1, W, N, PRIx##W);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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#define TEST_VCVT_FP16(T1, T2, W1, W2, N) \
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VECT_VAR(vector_res, T1, W1, N) = \
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vcvt_##T2##W1##_##T2##W2(VECT_VAR(vector, T1, W2, N)); \
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vst1q_##T2##W1(VECT_VAR(result, T1, W1, N), \
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VECT_VAR(vector_res, T1, W1, N)); \
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DUMP_FP(TEST_MSG, T1, W1, N, PRIx##W1);
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#define TEST_VCVT_2FP16(T1, T2, W1, W2, N) \
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VECT_VAR(vector_res, T1, W1, N) = \
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vcvt_##T2##W1##_##T2##W2(VECT_VAR(vector, T1, W2, N)); \
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vst1_##T2##W1(VECT_VAR(result, T1, W1, N), \
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VECT_VAR(vector_res, T1, W1, N)); \
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DUMP_FP16(TEST_MSG, T1, W1, N, PRIx##W1);
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#endif
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#define TEST_VCVT_N(Q, T1, T2, W, N, TS1, TS2, V) \
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VECT_VAR(vector_res, T1, W, N) = \
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vcvt##Q##_n_##T2##W##_##TS2##W(VECT_VAR(vector, TS1, W, N), V); \
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vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
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VECT_VAR(vector_res, T1, W, N)); \
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DUMP(TEST_MSG, T1, W, N, PRIx##W);
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#define TEST_VCVT_N_FP(Q, T1, T2, W, N, TS1, TS2, V) \
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VECT_VAR(vector_res, T1, W, N) = \
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vcvt##Q##_n_##T2##W##_##TS2##W(VECT_VAR(vector, TS1, W, N), V); \
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vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
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VECT_VAR(vector_res, T1, W, N)); \
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DUMP_FP(TEST_MSG, T1, W, N, PRIx##W);
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/* With ARM RVCT, we need to declare variables before any executable
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statement */
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DECL_VARIABLE_ALL_VARIANTS(vector);
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DECL_VARIABLE_ALL_VARIANTS(vector_res);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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DECL_VARIABLE(vector_init, uint, 16, 4);
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DECL_VARIABLE(vector_init, uint, 16, 8);
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DECL_VARIABLE(vector, float, 16, 4);
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DECL_VARIABLE(vector, float, 16, 8);
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DECL_VARIABLE(vector_res, float, 16, 4);
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DECL_VARIABLE(vector_res, float, 16, 8);
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#endif
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clean_results ();
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/* Initialize input "vector" from "buffer" */
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TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
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VLOAD(vector, buffer, , float, f, 32, 2);
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VLOAD(vector, buffer, q, float, f, 32, 4);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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VLOAD(vector, buffer, , float, f, 16, 4);
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VLOAD(vector, buffer, q, float, f, 16, 8);
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#endif
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/* Make sure some elements have a fractional part, to exercise
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integer conversions */
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TEST_VSET_LANE(vector, , float, f, 32, 2, 0, -15.3f);
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TEST_VSET_LANE(vector, , float, f, 32, 2, 1, 5.3f);
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TEST_VSET_LANE(vector, q, float, f, 32, 4, 2, -15.3f);
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TEST_VSET_LANE(vector, q, float, f, 32, 4, 3, 5.3f);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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/* FP16 tests. */
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/* There is no vdup_n_f16, so we need another initialization
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method. */
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/* Use all lanes with values of different types: first, a "standard"
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positive number, a "standard" negative one, and +0 and -0. */
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TEST_VSET_LANE(vector_init, , uint, u, 16, 4, 0, 0x4b90 /* 15.125 */);
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TEST_VSET_LANE(vector_init, , uint, u, 16, 4, 1, 0xcb90 /* -15.125 */);
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TEST_VSET_LANE(vector_init, , uint, u, 16, 4, 2, 0 /* 0 */);
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TEST_VSET_LANE(vector_init, , uint, u, 16, 4, 3, 0x8000 /* -0 */);
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VECT_VAR(vector, float, 16, 4) =
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vreinterpret_f16_u16(VECT_VAR(vector_init, uint, 16, 4));
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#endif
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/* The same result buffers are used multiple times, so we output
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them before overwriting them */
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fprintf(ref_file, "\n%s output:\n", TEST_MSG);
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fprintf(gcc_tests_file, "\n%s output:\n", TEST_MSG);
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/* vcvt_f32_xx */
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TEST_VCVT_FP(, float, f, 32, 2, int, s);
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TEST_VCVT_FP(, float, f, 32, 2, uint, u);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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TEST_VCVT_FP16(float, f, 32, 16, 4);
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#endif
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/* vcvtq_f32_xx */
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TEST_VCVT_FP(q, float, f, 32, 4, int, s);
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TEST_VCVT_FP(q, float, f, 32, 4, uint, u);
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/* vcvt_xx_f32 */
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TEST_VCVT(, int, s, 32, 2, float, f);
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TEST_VCVT(, uint, u, 32, 2, float, f);
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TEST_VSET_LANE(vector, q, float, f, 32, 4, 0, 0.0f);
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TEST_VSET_LANE(vector, q, float, f, 32, 4, 1, -0.0f);
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TEST_VSET_LANE(vector, q, float, f, 32, 4, 2, 15.12f);
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TEST_VSET_LANE(vector, q, float, f, 32, 4, 3, -15.12f);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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TEST_VCVT_2FP16(float, f, 16, 32, 4);
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#endif
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/* vcvtq_xx_f32 */
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TEST_VCVT(q, int, s, 32, 4, float, f);
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TEST_VCVT(q, uint, u, 32, 4, float, f);
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/* The same result buffers are used multiple times, so output them
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before overwriting them */
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#undef TEST_MSG
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#define TEST_MSG "VCVT_N/VCVTQ_N"
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fprintf(ref_file, "\n%s output:\n", TEST_MSG);
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fprintf(gcc_tests_file, "\n%s output:\n", TEST_MSG);
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/* vcvt_n_f32_xx */
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TEST_VCVT_N_FP(, float, f, 32, 2, int, s, 2);
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TEST_VCVT_N_FP(, float, f, 32, 2, uint, u, 7);
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/* vcvtq_n_f32_xx */
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TEST_VCVT_N_FP(q, float, f, 32, 4, int, s, 30);
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TEST_VCVT_N_FP(q, float, f, 32, 4, uint, u, 12);
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/* vcvt_n_xx_f32 */
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TEST_VCVT_N(, int, s, 32, 2, float, f, 20);
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TEST_VCVT_N(, uint, u, 32, 2, float, f, 2);
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/* vcvtq_n_xx_f32 */
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TEST_VCVT_N(q, int, s, 32, 4, float, f, 13);
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TEST_VCVT_N(q, uint, u, 32, 4, float, f, 1);
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/* Check rounding */
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#undef TEST_MSG
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#define TEST_MSG "VCVT/VCVTQ"
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fprintf(ref_file, "\n%s output:\n", TEST_MSG " (check rounding)");
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VDUP(vector, , float, f, 32, 2, 10.4f);
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VDUP(vector, q, float, f, 32, 4, 125.9f);
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/* vcvt_xx_f32 */
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TEST_VCVT(, int, s, 32, 2, float, f);
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TEST_VCVT(, uint, u, 32, 2, float, f);
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/* vcvtq_xx_f32 */
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TEST_VCVT(q, int, s, 32, 4, float, f);
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TEST_VCVT(q, uint, u, 32, 4, float, f);
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#undef TEST_MSG
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#define TEST_MSG "VCVT_N/VCVTQ_N"
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fprintf(ref_file, "\n%s output:\n", TEST_MSG " (check rounding)");
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/* vcvt_n_xx_f32 */
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TEST_VCVT_N(, int, s, 32, 2, float, f, 20);
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TEST_VCVT_N(, uint, u, 32, 2, float, f, 20);
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/* vcvtq_n_xx_f32 */
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TEST_VCVT_N(q, int, s, 32, 4, float, f, 13);
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TEST_VCVT_N(q, uint, u, 32, 4, float, f, 13);
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#undef TEST_MSG
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#define TEST_MSG "VCVT_N/VCVTQ_N"
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fprintf(ref_file, "\n%s output:\n", TEST_MSG " (check saturation)");
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/* vcvt_n_xx_f32 */
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TEST_VCVT_N(, int, s, 32, 2, float, f, 31);
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/* vcvtq_n_xx_f32 */
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TEST_VCVT_N(q, int, s, 32, 4, float, f, 31);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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#undef TEST_MSG
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#define TEST_MSG "VCVT FP16"
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fprintf(ref_file, "\n%s output:\n", TEST_MSG " (check fp16-fp32 inf/nan/denormal)");
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TEST_VSET_LANE(vector_init, , uint, u, 16, 4, 0, 0x0390 /* DENORMAL */);
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TEST_VSET_LANE(vector_init, , uint, u, 16, 4, 1, 0x7c00 /* inf */);
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TEST_VSET_LANE(vector_init, , uint, u, 16, 4, 2, 0x7e00 /* nan */);
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TEST_VSET_LANE(vector_init, , uint, u, 16, 4, 3, 0xfc00 /* -inf */);
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VECT_VAR(vector, float, 16, 4) =
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vreinterpret_f16_u16(VECT_VAR(vector_init, uint, 16, 4));
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TEST_VCVT_FP16(float, f, 32, 16, 4);
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fprintf(ref_file, "\n%s output:\n", TEST_MSG " (check fp32-fp16 inf/nan)");
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TEST_VSET_LANE(vector, q, float, f, 32, 4, 0, NAN);
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TEST_VSET_LANE(vector, q, float, f, 32, 4, 1, HUGE_VALF);
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TEST_VSET_LANE(vector, q, float, f, 32, 4, 2, -HUGE_VALF);
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TEST_VSET_LANE(vector, q, float, f, 32, 4, 3, -0.0f);
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TEST_VCVT_2FP16(float, f, 16, 32, 4);
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#endif
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}
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