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97 lines
3.5 KiB
97 lines
3.5 KiB
/*
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Copyright (c) 2009, 2010, 2011, 2013 STMicroelectronics
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Written by Christophe Lyon
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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#define INSN_NAME vsli
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#define TEST_MSG "VSLI_N"
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/* Extra tests for functions requiring corner cases tests */
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void vsli_extra(void);
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#define EXTRA_TESTS vsli_extra
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#include "ref_vsXi_n.c"
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void vsli_extra(void)
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{
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/* Test cases with maximum shift amount (this amount is different
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from vsri). */
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/* With ARM RVCT, we need to declare variables before any executable
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statement */
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DECL_VARIABLE_ALL_VARIANTS(vector);
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DECL_VARIABLE_ALL_VARIANTS(vector2);
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DECL_VARIABLE_ALL_VARIANTS(vector_res);
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clean_results ();
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/* Initialize input "vector" from "buffer" */
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TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
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/* Fill input vector2 with arbitrary values */
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VDUP(vector2, , int, s, 8, 8, 2);
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VDUP(vector2, , int, s, 16, 4, -4);
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VDUP(vector2, , int, s, 32, 2, 3);
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VDUP(vector2, , int, s, 64, 1, 100);
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VDUP(vector2, , uint, u, 8, 8, 20);
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VDUP(vector2, , uint, u, 16, 4, 30);
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VDUP(vector2, , uint, u, 32, 2, 40);
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VDUP(vector2, , uint, u, 64, 1, 2);
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VDUP(vector2, , poly, p, 8, 8, 20);
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VDUP(vector2, , poly, p, 16, 4, 30);
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VDUP(vector2, q, int, s, 8, 16, -10);
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VDUP(vector2, q, int, s, 16, 8, -20);
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VDUP(vector2, q, int, s, 32, 4, -30);
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VDUP(vector2, q, int, s, 64, 2, 24);
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VDUP(vector2, q, uint, u, 8, 16, 12);
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VDUP(vector2, q, uint, u, 16, 8, 3);
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VDUP(vector2, q, uint, u, 32, 4, 55);
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VDUP(vector2, q, uint, u, 64, 2, 3);
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VDUP(vector2, q, poly, p, 8, 16, 12);
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VDUP(vector2, q, poly, p, 16, 8, 3);
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/* Use maximum allowed shift amount */
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TEST_VSXI_N(INSN_NAME, , int, s, 8, 8, 7);
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TEST_VSXI_N(INSN_NAME, , int, s, 16, 4, 15);
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TEST_VSXI_N(INSN_NAME, , int, s, 32, 2, 31);
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TEST_VSXI_N(INSN_NAME, , int, s, 64, 1, 63);
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TEST_VSXI_N(INSN_NAME, , uint, u, 8, 8, 7);
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TEST_VSXI_N(INSN_NAME, , uint, u, 16, 4, 15);
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TEST_VSXI_N(INSN_NAME, , uint, u, 32, 2, 31);
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TEST_VSXI_N(INSN_NAME, , uint, u, 64, 1, 63);
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TEST_VSXI_N(INSN_NAME, , poly, p, 8, 8, 7);
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TEST_VSXI_N(INSN_NAME, , poly, p, 16, 4, 15);
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TEST_VSXI_N(INSN_NAME, q, int, s, 8, 16, 7);
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TEST_VSXI_N(INSN_NAME, q, int, s, 16, 8, 15);
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TEST_VSXI_N(INSN_NAME, q, int, s, 32, 4, 31);
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TEST_VSXI_N(INSN_NAME, q, int, s, 64, 2, 63);
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TEST_VSXI_N(INSN_NAME, q, uint, u, 8, 16, 7);
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TEST_VSXI_N(INSN_NAME, q, uint, u, 16, 8, 15);
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TEST_VSXI_N(INSN_NAME, q, uint, u, 32, 4, 31);
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TEST_VSXI_N(INSN_NAME, q, uint, u, 64, 2, 63);
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TEST_VSXI_N(INSN_NAME, q, poly, p, 8, 16, 7);
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TEST_VSXI_N(INSN_NAME, q, poly, p, 16, 8, 15);
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dump_results_hex2 (TEST_MSG, "max shift amount");
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}
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