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150 lines
4.2 KiB
150 lines
4.2 KiB
/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* The .data section gets copied from ROM to RAM at runtime.
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* Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes
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* aligned regions in it.
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* Its VMA must be page-aligned as it marks the first read/write page.
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*/
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#define DATA_ALIGN 16
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#include <common/bl_common.ld.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
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OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
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ENTRY(bl1_entrypoint)
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MEMORY {
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ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE
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RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
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}
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SECTIONS
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{
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. = BL1_RO_BASE;
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ASSERT(. == ALIGN(PAGE_SIZE),
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"BL1_RO_BASE address is not aligned on a page boundary.")
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#if SEPARATE_CODE_AND_RODATA
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.text . : {
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__TEXT_START__ = .;
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*bl1_entrypoint.o(.text*)
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*(SORT_BY_ALIGNMENT(.text*))
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*(.vectors)
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. = ALIGN(PAGE_SIZE);
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__TEXT_END__ = .;
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} >ROM
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/* .ARM.extab and .ARM.exidx are only added because Clang need them */
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.ARM.extab . : {
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} >ROM
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.ARM.exidx . : {
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} >ROM
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.rodata . : {
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__RODATA_START__ = .;
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*(SORT_BY_ALIGNMENT(.rodata*))
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RODATA_COMMON
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/*
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* No need to pad out the .rodata section to a page boundary. Next is
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* the .data section, which can mapped in ROM with the same memory
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* attributes as the .rodata section.
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*
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* Pad out to 16 bytes though as .data section needs to be 16 byte
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* aligned and lld does not align the LMA to the aligment specified
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* on the .data section.
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*/
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__RODATA_END__ = .;
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. = ALIGN(16);
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} >ROM
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#else
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ro . : {
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__RO_START__ = .;
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*bl1_entrypoint.o(.text*)
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*(SORT_BY_ALIGNMENT(.text*))
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*(SORT_BY_ALIGNMENT(.rodata*))
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RODATA_COMMON
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*(.vectors)
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__RO_END__ = .;
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/*
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* Pad out to 16 bytes as .data section needs to be 16 byte aligned and
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* lld does not align the LMA to the aligment specified on the .data
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* section.
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*/
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. = ALIGN(16);
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} >ROM
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#endif
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ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
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"cpu_ops not defined for this platform.")
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. = BL1_RW_BASE;
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ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
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"BL1_RW_BASE address is not aligned on a page boundary.")
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DATA_SECTION >RAM AT>ROM
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__DATA_RAM_START__ = __DATA_START__;
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__DATA_RAM_END__ = __DATA_END__;
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STACK_SECTION >RAM
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BSS_SECTION >RAM
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XLAT_TABLE_SECTION >RAM
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#if USE_COHERENT_MEM
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/*
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* The base address of the coherent memory section must be page-aligned (4K)
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* to guarantee that the coherent data are stored on their own pages and
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* are not mixed with normal data. This is required to set up the correct
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* memory attributes for the coherent data page tables.
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*/
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coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
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__COHERENT_RAM_START__ = .;
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*(tzfw_coherent_mem)
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__COHERENT_RAM_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked
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* as device memory. No other unexpected data must creep in.
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* Ensure the rest of the current memory page is unused.
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*/
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. = ALIGN(PAGE_SIZE);
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__COHERENT_RAM_END__ = .;
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} >RAM
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#endif
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__BL1_RAM_START__ = ADDR(.data);
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__BL1_RAM_END__ = .;
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__DATA_ROM_START__ = LOADADDR(.data);
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__DATA_SIZE__ = SIZEOF(.data);
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/*
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* The .data section is the last PROGBITS section so its end marks the end
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* of BL1's actual content in Trusted ROM.
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*/
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__BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__;
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ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT,
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"BL1's ROM content has exceeded its limit.")
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__BSS_SIZE__ = SIZEOF(.bss);
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#if USE_COHERENT_MEM
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__COHERENT_RAM_UNALIGNED_SIZE__ =
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__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
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#endif
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ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
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}
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