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117 lines
4.4 KiB
117 lines
4.4 KiB
/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <bl32/tsp/tsp.h>
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#include <common/debug.h>
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#include <plat/common/platform.h>
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#include "tsp_private.h"
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/*******************************************************************************
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* This function updates the TSP statistics for S-EL1 interrupts handled
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* synchronously i.e the ones that have been handed over by the TSPD. It also
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* keeps count of the number of times control was passed back to the TSPD
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* after handling the interrupt. In the future it will be possible that the
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* TSPD hands over an S-EL1 interrupt to the TSP but does not expect it to
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* return execution. This statistic will be useful to distinguish between these
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* two models of synchronous S-EL1 interrupt handling. The 'elr_el3' parameter
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* contains the address of the instruction in normal world where this S-EL1
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* interrupt was generated.
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******************************************************************************/
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void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3)
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{
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uint32_t linear_id = plat_my_core_pos();
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tsp_stats[linear_id].sync_sel1_intr_count++;
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if (type == TSP_HANDLE_SEL1_INTR_AND_RETURN)
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tsp_stats[linear_id].sync_sel1_intr_ret_count++;
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#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
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spin_lock(&console_lock);
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VERBOSE("TSP: cpu 0x%lx sync s-el1 interrupt request from 0x%llx\n",
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read_mpidr(), elr_el3);
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VERBOSE("TSP: cpu 0x%lx: %d sync s-el1 interrupt requests,"
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" %d sync s-el1 interrupt returns\n",
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read_mpidr(),
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tsp_stats[linear_id].sync_sel1_intr_count,
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tsp_stats[linear_id].sync_sel1_intr_ret_count);
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spin_unlock(&console_lock);
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#endif
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}
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/******************************************************************************
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* This function is invoked when a non S-EL1 interrupt is received and causes
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* the preemption of TSP. This function returns TSP_PREEMPTED and results
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* in the control being handed over to EL3 for handling the interrupt.
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*****************************************************************************/
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int32_t tsp_handle_preemption(void)
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{
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uint32_t linear_id = plat_my_core_pos();
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tsp_stats[linear_id].preempt_intr_count++;
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#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
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spin_lock(&console_lock);
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VERBOSE("TSP: cpu 0x%lx: %d preempt interrupt requests\n",
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read_mpidr(), tsp_stats[linear_id].preempt_intr_count);
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spin_unlock(&console_lock);
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#endif
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return TSP_PREEMPTED;
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}
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/*******************************************************************************
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* TSP interrupt handler is called as a part of both synchronous and
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* asynchronous handling of TSP interrupts. Currently the physical timer
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* interrupt is the only S-EL1 interrupt that this handler expects. It returns
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* 0 upon successfully handling the expected interrupt and all other
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* interrupts are treated as normal world or EL3 interrupts.
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******************************************************************************/
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int32_t tsp_common_int_handler(void)
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{
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uint32_t linear_id = plat_my_core_pos(), id;
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/*
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* Get the highest priority pending interrupt id and see if it is the
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* secure physical generic timer interrupt in which case, handle it.
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* Otherwise throw this interrupt at the EL3 firmware.
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*
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* There is a small time window between reading the highest priority
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* pending interrupt and acknowledging it during which another
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* interrupt of higher priority could become the highest pending
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* interrupt. This is not expected to happen currently for TSP.
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*/
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id = plat_ic_get_pending_interrupt_id();
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/* TSP can only handle the secure physical timer interrupt */
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if (id != TSP_IRQ_SEC_PHY_TIMER)
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return tsp_handle_preemption();
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/*
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* Acknowledge and handle the secure timer interrupt. Also sanity check
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* if it has been preempted by another interrupt through an assertion.
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*/
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id = plat_ic_acknowledge_interrupt();
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assert(id == TSP_IRQ_SEC_PHY_TIMER);
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tsp_generic_timer_handler();
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plat_ic_end_of_interrupt(id);
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/* Update the statistics and print some messages */
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tsp_stats[linear_id].sel1_intr_count++;
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#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
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spin_lock(&console_lock);
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VERBOSE("TSP: cpu 0x%lx handled S-EL1 interrupt %d\n",
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read_mpidr(), id);
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VERBOSE("TSP: cpu 0x%lx: %d S-EL1 requests\n",
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read_mpidr(), tsp_stats[linear_id].sel1_intr_count);
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spin_unlock(&console_lock);
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#endif
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return 0;
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}
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