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110 lines
3.0 KiB
110 lines
3.0 KiB
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <drivers/delay_timer.h>
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#include <drivers/marvell/aro.h>
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#include <lib/mmio.h>
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#include <a8k_plat_def.h>
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/* Notify bootloader on DRAM setup */
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#define AP807_CPU_ARO_CTRL(cluster) \
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(MVEBU_RFU_BASE + 0x82A8 + (0xA58 * (cluster)))
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/* 0 - ARO clock is enabled, 1 - ARO clock is disabled */
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#define AP807_CPU_ARO_CLK_EN_OFFSET 0
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#define AP807_CPU_ARO_CLK_EN_MASK (0x1 << AP807_CPU_ARO_CLK_EN_OFFSET)
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/* 0 - ARO is the clock source, 1 - PLL is the clock source */
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#define AP807_CPU_ARO_SEL_PLL_OFFSET 5
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#define AP807_CPU_ARO_SEL_PLL_MASK (0x1 << AP807_CPU_ARO_SEL_PLL_OFFSET)
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/* AP807 clusters count */
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#define AP807_CLUSTER_NUM 2
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/* PLL frequency values */
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#define PLL_FREQ_1200 0x2AE5F002 /* 1200 */
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#define PLL_FREQ_2000 0x2FC9F002 /* 2000 */
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#define PLL_FREQ_2200 0x2AC57001 /* 2200 */
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#define PLL_FREQ_2400 0x2AE5F001 /* 2400 */
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/* CPU PLL control registers */
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#define AP807_CPU_PLL_CTRL(cluster) \
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(MVEBU_RFU_BASE + 0x82E0 + (0x8 * (cluster)))
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#define AP807_CPU_PLL_PARAM(cluster) AP807_CPU_PLL_CTRL(cluster)
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#define AP807_CPU_PLL_CFG(cluster) (AP807_CPU_PLL_CTRL(cluster) + 0x4)
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#define AP807_CPU_PLL_CFG_BYPASS_MODE (0x1)
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#define AP807_CPU_PLL_FRC_DSCHG (0x2)
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#define AP807_CPU_PLL_CFG_USE_REG_FILE (0x1 << 9)
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static void pll_set_freq(unsigned int freq_val)
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{
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int i;
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if (freq_val != PLL_FREQ_2200)
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return;
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for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) {
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/* Set parameter of cluster i PLL to 2.2GHz */
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mmio_write_32(AP807_CPU_PLL_PARAM(i), freq_val);
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/* Set apll_lpf_frc_dschg - Control
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* voltage of internal VCO is discharged
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*/
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mmio_write_32(AP807_CPU_PLL_CFG(i),
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AP807_CPU_PLL_FRC_DSCHG);
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/* Set use_rf_conf load PLL parameter from register */
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mmio_write_32(AP807_CPU_PLL_CFG(i),
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AP807_CPU_PLL_FRC_DSCHG |
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AP807_CPU_PLL_CFG_USE_REG_FILE);
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/* Un-set apll_lpf_frc_dschg */
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mmio_write_32(AP807_CPU_PLL_CFG(i),
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AP807_CPU_PLL_CFG_USE_REG_FILE);
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}
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}
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/* Switch to ARO from PLL in ap807 */
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static void aro_to_pll(void)
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{
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unsigned int reg;
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int i;
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for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) {
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/* switch from ARO to PLL */
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reg = mmio_read_32(AP807_CPU_ARO_CTRL(i));
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reg |= AP807_CPU_ARO_SEL_PLL_MASK;
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mmio_write_32(AP807_CPU_ARO_CTRL(i), reg);
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mdelay(100);
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/* disable ARO clk driver */
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reg = mmio_read_32(AP807_CPU_ARO_CTRL(i));
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reg |= (AP807_CPU_ARO_CLK_EN_MASK);
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mmio_write_32(AP807_CPU_ARO_CTRL(i), reg);
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}
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}
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/* switch from ARO to PLL
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* in case of default frequency option, configure PLL registers
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* to be aligned with new default frequency.
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*/
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void ap807_clocks_init(unsigned int freq_option)
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{
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/* Modifications in frequency table:
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* 0x0: 764x: change to 2000 MHz.
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* 0x2: 744x change to 1800 MHz, 764x change to 2200/2400.
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* 0x3: 3900/744x/764x change to 1200 MHz.
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*/
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if (freq_option == CPU_2200_DDR_1200_RCLK_1200)
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pll_set_freq(PLL_FREQ_2200);
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/* Switch from ARO to PLL */
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aro_to_pll();
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}
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