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231 lines
5.2 KiB
231 lines
5.2 KiB
/*
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <services/sdei_flags.h>
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#define LEVEL 0
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#define EDGE 2
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#define SDEI_NORMAL 0x70
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#define HIGHEST_SEC 0
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/memreserve/ 0x80000000 0x00010000;
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/ {
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};
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/ {
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model = "FVP Base";
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compatible = "arm,vfp-base", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
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method = "smc";
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cpu_suspend = <0xc4000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0xc4000003>;
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sys_poweroff = <0x84000008>;
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sys_reset = <0x84000009>;
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max-pwr-lvl = <2>;
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};
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#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF
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firmware {
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#if SDEI_IN_FCONF
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sdei {
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compatible = "arm,sdei-1.0";
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method = "smc";
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private_event_count = <3>;
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shared_event_count = <3>;
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/*
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* Each event descriptor has typically 3 fields:
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* 1. Event number
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* 2. Interrupt number the event is bound to or
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* if event is dynamic, specified as SDEI_DYN_IRQ
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* 3. Bit map of event flags
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*/
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private_events = <1000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
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<1001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
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<1002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>;
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shared_events = <2000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
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<2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
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<2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>;
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};
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#endif /* SDEI_IN_FCONF */
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#if SEC_INT_DESC_IN_FCONF
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sec_interrupts {
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compatible = "arm,secure_interrupt_desc";
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/* Number of G0 and G1 secure interrupts defined by the platform */
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g0_intr_cnt = <2>;
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g1s_intr_cnt = <9>;
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. Each interrupt property descriptor has 3 fields:
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* 1. Interrupt number
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* 2. Interrupt priority
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* 3. Type of interrupt (Edge or Level configured)
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*/
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g0_intr_desc = < 8 SDEI_NORMAL EDGE>,
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<14 HIGHEST_SEC EDGE>;
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g1s_intr_desc = < 9 HIGHEST_SEC EDGE>,
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<10 HIGHEST_SEC EDGE>,
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<11 HIGHEST_SEC EDGE>,
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<12 HIGHEST_SEC EDGE>,
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<13 HIGHEST_SEC EDGE>,
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<15 HIGHEST_SEC EDGE>,
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<29 HIGHEST_SEC LEVEL>,
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<56 HIGHEST_SEC LEVEL>,
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<57 HIGHEST_SEC LEVEL>;
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};
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#endif /* SEC_INT_DESC_IN_FCONF */
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};
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#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU_MAP
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idle-states {
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entry-method = "arm,psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <40>;
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exit-latency-us = <100>;
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min-residency-us = <150>;
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};
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x1010000>;
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entry-latency-us = <500>;
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exit-latency-us = <1000>;
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min-residency-us = <2500>;
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};
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};
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CPUS
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x7F000000>,
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<0x00000008 0x80000000 0 0x80000000>;
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};
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gic: interrupt-controller@2f000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0x2f000000 0 0x10000>, // GICD
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<0x0 0x2f100000 0 0x200000>, // GICR
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<0x0 0x2c000000 0 0x2000>, // GICC
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<0x0 0x2c010000 0 0x2000>, // GICH
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<0x0 0x2c02f000 0 0x2000>; // GICV
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interrupts = <1 9 4>;
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its: its@2f020000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xff01>,
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<1 14 0xff01>,
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<1 11 0xff01>,
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<1 10 0xff01>;
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clock-frequency = <100000000>;
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};
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timer@2a810000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x2a810000 0x0 0x10000>;
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clock-frequency = <100000000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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frame@2a830000 {
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frame-number = <1>;
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interrupts = <0 26 4>;
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reg = <0x0 0x2a830000 0x0 0x10000>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <0 60 4>,
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<0 61 4>,
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<0 62 4>,
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<0 63 4>;
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};
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smb@0,0 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0 0x08000000 0x04000000>,
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<1 0 0 0x14000000 0x04000000>,
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<2 0 0 0x18000000 0x04000000>,
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<3 0 0 0x1c000000 0x04000000>,
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<4 0 0 0x0c000000 0x04000000>,
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<5 0 0 0x10000000 0x04000000>;
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#include "rtsm_ve-motherboard.dtsi"
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};
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panels {
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panel {
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compatible = "panel";
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mode = "XVGA";
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refresh = <60>;
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xres = <1024>;
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yres = <768>;
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pixclock = <15748>;
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left_margin = <152>;
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right_margin = <48>;
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upper_margin = <23>;
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lower_margin = <3>;
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hsync_len = <104>;
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vsync_len = <4>;
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sync = <0>;
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vmode = "FB_VMODE_NONINTERLACED";
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tim2 = "TIM2_BCD", "TIM2_IPC";
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cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
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caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
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bpp = <16>;
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};
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};
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};
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