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156 lines
3.9 KiB
156 lines
3.9 KiB
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/interrupt_props.h>
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#include <drivers/arm/cci.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/pl011.h>
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#include <lib/mmio.h>
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#include <hi6220.h>
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#include <hikey_def.h>
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#include <hisi_ipc.h>
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#include <hisi_pwrc.h>
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#include "hikey_private.h"
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static entry_point_info_t bl32_ep_info;
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static entry_point_info_t bl33_ep_info;
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static console_t console;
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/******************************************************************************
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* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
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* interrupts.
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*****************************************************************************/
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static const interrupt_prop_t g0_interrupt_props[] = {
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INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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};
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/*
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* Ideally `arm_gic_data` structure definition should be a `const` but it is
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* kept as modifiable for overwriting with different GICD and GICC base when
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* running on FVP with VE memory map.
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*/
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gicv2_driver_data_t hikey_gic_data = {
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.gicd_base = PLAT_ARM_GICD_BASE,
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.gicc_base = PLAT_ARM_GICC_BASE,
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.interrupt_props = g0_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
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};
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static const int cci_map[] = {
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CCI400_SL_IFACE3_CLUSTER_IX,
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CCI400_SL_IFACE4_CLUSTER_IX
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};
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
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/* None of the images on this platform can have 0x0 as the entrypoint */
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if (next_image_info->pc)
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return next_image_info;
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return NULL;
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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void *from_bl2;
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from_bl2 = (void *) arg0;
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/* Initialize the console to provide early debug support */
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console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ,
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PL011_BAUDRATE, &console);
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/* Initialize CCI driver */
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cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map));
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
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/*
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* Check params passed from BL2 should not be NULL,
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*/
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bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
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assert(params_from_bl2 != NULL);
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assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
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assert(params_from_bl2->h.version >= VERSION_2);
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bl_params_node_t *bl_params = params_from_bl2->head;
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/*
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* Copy BL33 and BL32 (if present), entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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while (bl_params) {
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if (bl_params->image_id == BL32_IMAGE_ID)
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bl32_ep_info = *bl_params->ep_info;
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if (bl_params->image_id == BL33_IMAGE_ID)
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bl33_ep_info = *bl_params->ep_info;
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bl_params = bl_params->next_params_info;
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}
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if (bl33_ep_info.pc == 0)
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panic();
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}
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void bl31_plat_arch_setup(void)
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{
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hikey_init_mmu_el3(BL31_BASE,
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BL31_LIMIT - BL31_BASE,
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BL_CODE_BASE,
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BL_CODE_END,
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BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END);
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}
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/* Initialize EDMAC controller with non-secure mode. */
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static void hikey_edma_init(void)
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{
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int i;
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uint32_t non_secure;
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non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC;
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mmio_write_32(EDMAC_SEC_CTRL, non_secure);
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for (i = 0; i < EDMAC_CHANNEL_NUMS; i++) {
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mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18));
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}
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}
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void bl31_platform_setup(void)
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{
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/* Initialize the GIC driver, cpu and distributor interfaces */
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gicv2_driver_init(&hikey_gic_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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hikey_edma_init();
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hisi_ipc_init();
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hisi_pwrc_setup();
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}
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void bl31_plat_runtime_setup(void)
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{
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}
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