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391 lines
10 KiB
391 lines
10 KiB
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <drivers/arm/pl061_gpio.h>
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#include <drivers/arm/sp804_delay_timer.h>
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#include <drivers/gpio.h>
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#include <lib/mmio.h>
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#include <hi6220.h>
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#include <hi6553.h>
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#include "hikey_private.h"
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void hikey_sp804_init(void)
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{
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uint32_t data;
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/* select the clock of dual timer0 */
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data = mmio_read_32(AO_SC_TIMER_EN0);
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while (data & 3) {
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data &= ~3;
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data |= 3 << 16;
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mmio_write_32(AO_SC_TIMER_EN0, data);
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data = mmio_read_32(AO_SC_TIMER_EN0);
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}
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/* enable the pclk of dual timer0 */
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data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4);
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while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0)) {
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mmio_write_32(AO_SC_PERIPH_CLKEN4, PCLK_TIMER1 | PCLK_TIMER0);
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data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4);
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}
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/* reset dual timer0 */
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data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
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mmio_write_32(AO_SC_PERIPH_RSTEN4, PCLK_TIMER1 | PCLK_TIMER0);
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do {
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data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
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} while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0));
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/* unreset dual timer0 */
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mmio_write_32(AO_SC_PERIPH_RSTDIS4, PCLK_TIMER1 | PCLK_TIMER0);
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do {
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data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
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} while ((data & PCLK_TIMER1) || (data & PCLK_TIMER0));
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sp804_timer_init(SP804_TIMER0_BASE, 10, 192);
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}
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void hikey_gpio_init(void)
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{
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pl061_gpio_init();
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pl061_gpio_register(GPIO0_BASE, 0);
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pl061_gpio_register(GPIO1_BASE, 1);
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pl061_gpio_register(GPIO2_BASE, 2);
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pl061_gpio_register(GPIO3_BASE, 3);
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pl061_gpio_register(GPIO4_BASE, 4);
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pl061_gpio_register(GPIO5_BASE, 5);
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pl061_gpio_register(GPIO6_BASE, 6);
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pl061_gpio_register(GPIO7_BASE, 7);
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pl061_gpio_register(GPIO8_BASE, 8);
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pl061_gpio_register(GPIO9_BASE, 9);
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pl061_gpio_register(GPIO10_BASE, 10);
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pl061_gpio_register(GPIO11_BASE, 11);
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pl061_gpio_register(GPIO12_BASE, 12);
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pl061_gpio_register(GPIO13_BASE, 13);
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pl061_gpio_register(GPIO14_BASE, 14);
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pl061_gpio_register(GPIO15_BASE, 15);
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pl061_gpio_register(GPIO16_BASE, 16);
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pl061_gpio_register(GPIO17_BASE, 17);
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pl061_gpio_register(GPIO18_BASE, 18);
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pl061_gpio_register(GPIO19_BASE, 19);
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/* Power on indicator LED (USER_LED1). */
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gpio_set_direction(32, GPIO_DIR_OUT); /* LED1 */
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gpio_set_value(32, GPIO_LEVEL_HIGH);
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gpio_set_direction(33, GPIO_DIR_OUT); /* LED2 */
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gpio_set_value(33, GPIO_LEVEL_LOW);
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gpio_set_direction(34, GPIO_DIR_OUT); /* LED3 */
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gpio_set_direction(35, GPIO_DIR_OUT); /* LED4 */
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}
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void hikey_pmussi_init(void)
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{
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uint32_t data;
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/* Initialize PWR_HOLD GPIO */
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gpio_set_direction(0, GPIO_DIR_OUT);
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gpio_set_value(0, GPIO_LEVEL_LOW);
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/*
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* After reset, PMUSSI stays in reset mode.
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* Now make it out of reset.
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*/
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mmio_write_32(AO_SC_PERIPH_RSTDIS4,
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AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N);
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do {
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data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
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} while (data & AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N);
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/* Set PMUSSI clock latency for read operation. */
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data = mmio_read_32(AO_SC_MCU_SUBSYS_CTRL3);
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data &= ~AO_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
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data |= AO_SC_MCU_SUBSYS_CTRL3_RCLK_3;
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mmio_write_32(AO_SC_MCU_SUBSYS_CTRL3, data);
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/* enable PMUSSI clock */
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data = AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU |
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AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_MCU;
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mmio_write_32(AO_SC_PERIPH_CLKEN5, data);
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data = AO_SC_PERIPH_CLKEN4_PCLK_PMUSSI;
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mmio_write_32(AO_SC_PERIPH_CLKEN4, data);
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gpio_set_value(0, GPIO_LEVEL_HIGH);
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}
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void hikey_hi6553_init(void)
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{
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uint8_t data;
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mmio_write_8(HI6553_PERI_EN_MARK, 0x1e);
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mmio_write_8(HI6553_NP_REG_ADJ1, 0);
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data = DISABLE6_XO_CLK_CONN | DISABLE6_XO_CLK_NFC |
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DISABLE6_XO_CLK_RF1 | DISABLE6_XO_CLK_RF2;
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mmio_write_8(HI6553_DISABLE6_XO_CLK, data);
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/* configure BUCK0 & BUCK1 */
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mmio_write_8(HI6553_BUCK01_CTRL2, 0x5e);
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mmio_write_8(HI6553_BUCK0_CTRL7, 0x10);
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mmio_write_8(HI6553_BUCK1_CTRL7, 0x10);
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mmio_write_8(HI6553_BUCK0_CTRL5, 0x1e);
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mmio_write_8(HI6553_BUCK1_CTRL5, 0x1e);
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mmio_write_8(HI6553_BUCK0_CTRL1, 0xfc);
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mmio_write_8(HI6553_BUCK1_CTRL1, 0xfc);
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/* configure BUCK2 */
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mmio_write_8(HI6553_BUCK2_REG1, 0x4f);
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mmio_write_8(HI6553_BUCK2_REG5, 0x99);
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mmio_write_8(HI6553_BUCK2_REG6, 0x45);
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mdelay(1);
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mmio_write_8(HI6553_VSET_BUCK2_ADJ, 0x22);
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mdelay(1);
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/* configure BUCK3 */
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mmio_write_8(HI6553_BUCK3_REG3, 0x02);
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mmio_write_8(HI6553_BUCK3_REG5, 0x99);
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mmio_write_8(HI6553_BUCK3_REG6, 0x41);
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mmio_write_8(HI6553_VSET_BUCK3_ADJ, 0x02);
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mdelay(1);
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/* configure BUCK4 */
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mmio_write_8(HI6553_BUCK4_REG2, 0x9a);
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mmio_write_8(HI6553_BUCK4_REG5, 0x99);
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mmio_write_8(HI6553_BUCK4_REG6, 0x45);
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/* configure LDO20 */
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mmio_write_8(HI6553_LDO20_REG_ADJ, 0x50);
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mmio_write_8(HI6553_NP_REG_CHG, 0x0f);
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mmio_write_8(HI6553_CLK_TOP0, 0x06);
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mmio_write_8(HI6553_CLK_TOP3, 0xc0);
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mmio_write_8(HI6553_CLK_TOP4, 0x00);
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/* configure LDO7 & LDO10 for SD slot */
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/* enable LDO7 */
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data = mmio_read_8(HI6553_LDO7_REG_ADJ);
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data = (data & 0xf8) | 0x2;
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mmio_write_8(HI6553_LDO7_REG_ADJ, data);
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mdelay(5);
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mmio_write_8(HI6553_ENABLE2_LDO1_8, 1 << 6);
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mdelay(5);
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/* enable LDO10 */
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data = mmio_read_8(HI6553_LDO10_REG_ADJ);
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data = (data & 0xf8) | 0x5;
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mmio_write_8(HI6553_LDO10_REG_ADJ, data);
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mdelay(5);
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mmio_write_8(HI6553_ENABLE3_LDO9_16, 1 << 1);
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mdelay(5);
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/* enable LDO15 */
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data = mmio_read_8(HI6553_LDO15_REG_ADJ);
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data = (data & 0xf8) | 0x4;
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mmio_write_8(HI6553_LDO15_REG_ADJ, data);
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mmio_write_8(HI6553_ENABLE3_LDO9_16, 1 << 6);
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mdelay(5);
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/* enable LDO19 */
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data = mmio_read_8(HI6553_LDO19_REG_ADJ);
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data |= 0x7;
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mmio_write_8(HI6553_LDO19_REG_ADJ, data);
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mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 2);
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mdelay(5);
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/* enable LDO21 */
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data = mmio_read_8(HI6553_LDO21_REG_ADJ);
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data = (data & 0xf8) | 0x3;
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mmio_write_8(HI6553_LDO21_REG_ADJ, data);
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mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 4);
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mdelay(5);
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/* enable LDO22 */
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data = mmio_read_8(HI6553_LDO22_REG_ADJ);
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data = (data & 0xf8) | 0x7;
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mmio_write_8(HI6553_LDO22_REG_ADJ, data);
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mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 5);
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mdelay(5);
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/* select 32.764KHz */
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mmio_write_8(HI6553_CLK19M2_600_586_EN, 0x01);
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/* Disable vbus_det interrupts */
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data = mmio_read_8(HI6553_IRQ2_MASK);
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data = data | 0x3;
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mmio_write_8(HI6553_IRQ2_MASK, data);
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}
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void init_mmc0_pll(void)
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{
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unsigned int data;
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/* select SYSPLL as the source of MMC0 */
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/* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
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mmio_write_32(PERI_SC_CLK_SEL0, 1 << 5 | 1 << 21);
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do {
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data = mmio_read_32(PERI_SC_CLK_SEL0);
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} while (!(data & (1 << 5)));
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/* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
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mmio_write_32(PERI_SC_CLK_SEL0, 1 << 29);
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do {
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data = mmio_read_32(PERI_SC_CLK_SEL0);
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} while (data & (1 << 13));
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mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 0));
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do {
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data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
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} while (!(data & (1 << 0)));
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data = mmio_read_32(PERI_SC_PERIPH_CLKEN12);
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data |= 1 << 1;
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mmio_write_32(PERI_SC_PERIPH_CLKEN12, data);
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do {
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mmio_write_32(PERI_SC_CLKCFG8BIT1, (1 << 7) | 0xb);
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data = mmio_read_32(PERI_SC_CLKCFG8BIT1);
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} while ((data & 0xb) != 0xb);
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}
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void reset_mmc0_clk(void)
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{
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unsigned int data;
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/* disable mmc0 bus clock */
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mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0);
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do {
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data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
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} while (data & PERI_CLK0_MMC0);
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/* enable mmc0 bus clock */
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mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0);
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do {
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data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
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} while (!(data & PERI_CLK0_MMC0));
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/* reset mmc0 clock domain */
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mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0);
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/* bypass mmc0 clock phase */
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data = mmio_read_32(PERI_SC_PERIPH_CTRL2);
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data |= 3;
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mmio_write_32(PERI_SC_PERIPH_CTRL2, data);
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/* disable low power */
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data = mmio_read_32(PERI_SC_PERIPH_CTRL13);
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data |= 1 << 3;
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mmio_write_32(PERI_SC_PERIPH_CTRL13, data);
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do {
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data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
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} while (!(data & PERI_RST0_MMC0));
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/* unreset mmc0 clock domain */
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mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0);
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do {
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data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
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} while (data & PERI_RST0_MMC0);
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}
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void init_media_clk(void)
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{
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unsigned int data, value;
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data = mmio_read_32(PMCTRL_MEDPLLCTRL);
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data |= 1;
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mmio_write_32(PMCTRL_MEDPLLCTRL, data);
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for (;;) {
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data = mmio_read_32(PMCTRL_MEDPLLCTRL);
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value = 1 << 28;
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if ((data & value) == value)
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break;
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}
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data = mmio_read_32(PERI_SC_PERIPH_CLKEN12);
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data = 1 << 10;
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mmio_write_32(PERI_SC_PERIPH_CLKEN12, data);
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}
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void init_mmc1_pll(void)
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{
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uint32_t data;
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/* select SYSPLL as the source of MMC1 */
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/* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
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mmio_write_32(PERI_SC_CLK_SEL0, 1 << 11 | 1 << 27);
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do {
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data = mmio_read_32(PERI_SC_CLK_SEL0);
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} while (!(data & (1 << 11)));
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/* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
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mmio_write_32(PERI_SC_CLK_SEL0, 1 << 30);
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do {
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data = mmio_read_32(PERI_SC_CLK_SEL0);
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} while (data & (1 << 14));
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mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 1));
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do {
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data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
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} while (!(data & (1 << 1)));
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data = mmio_read_32(PERI_SC_PERIPH_CLKEN12);
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data |= 1 << 2;
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mmio_write_32(PERI_SC_PERIPH_CLKEN12, data);
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do {
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/* 1.2GHz / 50 = 24MHz */
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mmio_write_32(PERI_SC_CLKCFG8BIT2, 0x31 | (1 << 7));
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data = mmio_read_32(PERI_SC_CLKCFG8BIT2);
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} while ((data & 0x31) != 0x31);
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}
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void reset_mmc1_clk(void)
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{
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unsigned int data;
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/* disable mmc1 bus clock */
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mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC1);
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do {
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data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
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} while (data & PERI_CLK0_MMC1);
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/* enable mmc1 bus clock */
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mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC1);
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do {
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data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
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} while (!(data & PERI_CLK0_MMC1));
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/* reset mmc1 clock domain */
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mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC1);
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/* bypass mmc1 clock phase */
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data = mmio_read_32(PERI_SC_PERIPH_CTRL2);
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data |= 3 << 2;
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mmio_write_32(PERI_SC_PERIPH_CTRL2, data);
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/* disable low power */
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data = mmio_read_32(PERI_SC_PERIPH_CTRL13);
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data |= 1 << 4;
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mmio_write_32(PERI_SC_PERIPH_CTRL13, data);
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do {
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data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
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} while (!(data & PERI_RST0_MMC1));
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/* unreset mmc0 clock domain */
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mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC1);
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do {
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data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
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} while (data & PERI_RST0_MMC1);
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}
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/* Initialize PLL of both eMMC and SD controllers. */
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void hikey_mmc_pll_init(void)
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{
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init_mmc0_pll();
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reset_mmc0_clk();
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init_media_clk();
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dsb();
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init_mmc1_pll();
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reset_mmc1_clk();
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}
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void hikey_rtc_init(void)
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{
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uint32_t data;
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data = mmio_read_32(AO_SC_PERIPH_CLKEN4);
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data |= AO_SC_PERIPH_RSTDIS4_RESET_RTC0_N;
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mmio_write_32(AO_SC_PERIPH_CLKEN4, data);
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}
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