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107 lines
3.4 KiB
107 lines
3.4 KiB
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef HIKEY_DEF_H
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#define HIKEY_DEF_H
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/* Always assume DDR is 1GB size. */
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#define DDR_BASE 0x0
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#define DDR_SIZE 0x40000000
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#define DEVICE_BASE 0xF4000000
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#define DEVICE_SIZE 0x05800000
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/* Memory location options for TSP */
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#define HIKEY_SRAM_ID 0
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#define HIKEY_DRAM_ID 1
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/*
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* DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several
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* regions
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* - Secure DDR (default is the top 16MB) used by OP-TEE
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* - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
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* - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
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* - Non-secure DDR (8MB) reserved for OP-TEE's future use
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*/
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#define DDR_SEC_SIZE 0x01000000
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#define DDR_SEC_BASE (DDR_BASE + DDR_SIZE - DDR_SEC_SIZE) /* 0x3F000000 */
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#define DDR_SDP_SIZE 0x00400000
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#define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \
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DDR_SDP_SIZE)
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#define SRAM_BASE 0xFFF80000
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#define SRAM_SIZE 0x00012000
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/*
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* PL011 related constants
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*/
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#define PL011_UART0_BASE 0xF8015000
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#define PL011_UART2_BASE 0xF7112000
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#define PL011_UART3_BASE 0xF7113000
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#define PL011_BAUDRATE 115200
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#define PL011_UART_CLK_IN_HZ 19200000
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#define HIKEY_USB_DESC_BASE (DDR_BASE + 0x00800000)
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#define HIKEY_USB_DESC_SIZE 0x00100000
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#define HIKEY_USB_DATA_BASE (DDR_BASE + 0x10000000)
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#define HIKEY_USB_DATA_SIZE 0x10000000
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#define HIKEY_FB_BUFFER_BASE (HIKEY_USB_DATA_BASE)
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#define HIKEY_FB_BUFFER_SIZE HIKEY_USB_DATA_SIZE
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#define HIKEY_FB_DOWNLOAD_BASE (HIKEY_FB_BUFFER_BASE + \
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HIKEY_FB_BUFFER_SIZE)
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#define HIKEY_FB_DOWNLOAD_SIZE HIKEY_USB_DATA_SIZE
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#define HIKEY_USB_DESC_IN_BASE (DDR_BASE + 0x00800000)
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#define HIKEY_USB_DESC_IN_SIZE 0x00040000
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#define HIKEY_USB_DESC_EP0_OUT_BASE (HIKEY_USB_DESC_IN_BASE + \
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HIKEY_USB_DESC_IN_SIZE)
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#define HIKEY_USB_DESC_EP0_OUT_SIZE 0x00040000
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#define HIKEY_USB_DESC_EPX_OUT_BASE (HIKEY_USB_DESC_EP0_OUT_BASE + \
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HIKEY_USB_DESC_EP0_OUT_SIZE)
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#define HIKEY_USB_DESC_EPX_OUT_SIZE 0x00080000
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#define HIKEY_MMC_DESC_BASE (DDR_BASE + 0x03000000)
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#define HIKEY_MMC_DESC_SIZE 0x00100000
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/*
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* HIKEY_MMC_DATA_BASE & HIKEY_MMC_DATA_SIZE are shared between fastboot
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* and eMMC driver. Since it could avoid to memory copy.
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* So this SRAM region is used twice. First, it's used in BL1 as temporary
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* buffer in eMMC driver. Second, it's used by MCU in BL2. The SRAM region
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* needs to be clear before used in BL2.
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*/
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#define HIKEY_MMC_DATA_BASE (DDR_BASE + 0x10000000)
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#define HIKEY_MMC_DATA_SIZE 0x20000000
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#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000)
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#define HIKEY_BL1_MMC_DESC_BASE (SRAM_BASE)
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#define HIKEY_BL1_MMC_DESC_SIZE 0x00001000
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#define HIKEY_BL1_MMC_DATA_BASE (HIKEY_BL1_MMC_DESC_BASE + \
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HIKEY_BL1_MMC_DESC_SIZE)
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#define HIKEY_BL1_MMC_DATA_SIZE 0x0000B000
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#define EMMC_BASE 0
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#define HIKEY_EMMC_RPMB_BASE (EMMC_BASE + 0)
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#define HIKEY_EMMC_RPMB_MAX_SIZE (128 << 10)
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#define HIKEY_EMMC_USERDATA_BASE (EMMC_BASE + 0)
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#define HIKEY_EMMC_USERDATA_MAX_SIZE (4 << 30)
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/*
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* GIC400 interrupt handling related constants
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*/
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#define IRQ_SEC_PHY_TIMER 29
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#define IRQ_SEC_SGI_0 8
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#define IRQ_SEC_SGI_1 9
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#define IRQ_SEC_SGI_2 10
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#define IRQ_SEC_SGI_3 11
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#define IRQ_SEC_SGI_4 12
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#define IRQ_SEC_SGI_5 13
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#define IRQ_SEC_SGI_6 14
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#define IRQ_SEC_SGI_7 15
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#define IRQ_SEC_SGI_8 16
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#endif /* HIKEY_DEF_H */
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