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309 lines
8.0 KiB
309 lines
8.0 KiB
/*
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdint.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <drivers/io/io_block.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include "uniphier.h"
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#define MMC_CMD_SWITCH 6
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#define MMC_CMD_SELECT_CARD 7
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#define MMC_CMD_SEND_CSD 9
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#define MMC_CMD_READ_MULTIPLE_BLOCK 18
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#define EXT_CSD_PART_CONF 179 /* R/W */
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#define MMC_RSP_PRESENT BIT(0)
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#define MMC_RSP_136 BIT(1) /* 136 bit response */
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#define MMC_RSP_CRC BIT(2) /* expect valid crc */
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#define MMC_RSP_BUSY BIT(3) /* card may send busy */
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#define MMC_RSP_OPCODE BIT(4) /* response contains opcode */
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#define MMC_RSP_NONE (0)
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#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
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#define MMC_RSP_R1b (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | \
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MMC_RSP_BUSY)
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#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
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#define MMC_RSP_R3 (MMC_RSP_PRESENT)
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#define MMC_RSP_R4 (MMC_RSP_PRESENT)
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#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
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#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
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#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
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#define SDHCI_DMA_ADDRESS 0x00
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#define SDHCI_BLOCK_SIZE 0x04
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#define SDHCI_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF))
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#define SDHCI_BLOCK_COUNT 0x06
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#define SDHCI_ARGUMENT 0x08
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#define SDHCI_TRANSFER_MODE 0x0C
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#define SDHCI_TRNS_DMA BIT(0)
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#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
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#define SDHCI_TRNS_ACMD12 BIT(2)
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#define SDHCI_TRNS_READ BIT(4)
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#define SDHCI_TRNS_MULTI BIT(5)
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#define SDHCI_COMMAND 0x0E
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#define SDHCI_CMD_RESP_MASK 0x03
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#define SDHCI_CMD_CRC 0x08
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#define SDHCI_CMD_INDEX 0x10
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#define SDHCI_CMD_DATA 0x20
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#define SDHCI_CMD_ABORTCMD 0xC0
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#define SDHCI_CMD_RESP_NONE 0x00
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#define SDHCI_CMD_RESP_LONG 0x01
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#define SDHCI_CMD_RESP_SHORT 0x02
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#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
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#define SDHCI_MAKE_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
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#define SDHCI_RESPONSE 0x10
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#define SDHCI_HOST_CONTROL 0x28
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#define SDHCI_CTRL_DMA_MASK 0x18
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#define SDHCI_CTRL_SDMA 0x00
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#define SDHCI_BLOCK_GAP_CONTROL 0x2A
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#define SDHCI_SOFTWARE_RESET 0x2F
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#define SDHCI_RESET_CMD 0x02
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#define SDHCI_RESET_DATA 0x04
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#define SDHCI_INT_STATUS 0x30
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#define SDHCI_INT_RESPONSE BIT(0)
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#define SDHCI_INT_DATA_END BIT(1)
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#define SDHCI_INT_DMA_END BIT(3)
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#define SDHCI_INT_ERROR BIT(15)
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#define SDHCI_SIGNAL_ENABLE 0x38
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/* RCA assigned by Boot ROM */
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#define UNIPHIER_EMMC_RCA 0x1000
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struct uniphier_mmc_cmd {
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unsigned int cmdidx;
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unsigned int resp_type;
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unsigned int cmdarg;
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unsigned int is_data;
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};
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struct uniphier_emmc_host {
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uintptr_t base;
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bool is_block_addressing;
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};
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static struct uniphier_emmc_host uniphier_emmc_host;
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static int uniphier_emmc_send_cmd(uintptr_t host_base,
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struct uniphier_mmc_cmd *cmd)
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{
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uint32_t mode = 0;
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uint32_t end_bit;
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uint32_t stat, flags, dma_addr;
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mmio_write_32(host_base + SDHCI_INT_STATUS, -1);
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mmio_write_32(host_base + SDHCI_SIGNAL_ENABLE, 0);
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mmio_write_32(host_base + SDHCI_ARGUMENT, cmd->cmdarg);
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if (cmd->is_data)
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mode = SDHCI_TRNS_DMA | SDHCI_TRNS_BLK_CNT_EN |
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SDHCI_TRNS_ACMD12 | SDHCI_TRNS_READ |
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SDHCI_TRNS_MULTI;
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mmio_write_16(host_base + SDHCI_TRANSFER_MODE, mode);
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if (!(cmd->resp_type & MMC_RSP_PRESENT))
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flags = SDHCI_CMD_RESP_NONE;
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else if (cmd->resp_type & MMC_RSP_136)
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flags = SDHCI_CMD_RESP_LONG;
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else if (cmd->resp_type & MMC_RSP_BUSY)
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flags = SDHCI_CMD_RESP_SHORT_BUSY;
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else
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flags = SDHCI_CMD_RESP_SHORT;
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if (cmd->resp_type & MMC_RSP_CRC)
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flags |= SDHCI_CMD_CRC;
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if (cmd->resp_type & MMC_RSP_OPCODE)
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flags |= SDHCI_CMD_INDEX;
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if (cmd->is_data)
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flags |= SDHCI_CMD_DATA;
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if (cmd->resp_type & MMC_RSP_BUSY || cmd->is_data)
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end_bit = SDHCI_INT_DATA_END;
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else
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end_bit = SDHCI_INT_RESPONSE;
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mmio_write_16(host_base + SDHCI_COMMAND,
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SDHCI_MAKE_CMD(cmd->cmdidx, flags));
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do {
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stat = mmio_read_32(host_base + SDHCI_INT_STATUS);
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if (stat & SDHCI_INT_ERROR)
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return -EIO;
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if (stat & SDHCI_INT_DMA_END) {
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mmio_write_32(host_base + SDHCI_INT_STATUS, stat);
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dma_addr = mmio_read_32(host_base + SDHCI_DMA_ADDRESS);
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mmio_write_32(host_base + SDHCI_DMA_ADDRESS, dma_addr);
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}
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} while (!(stat & end_bit));
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return 0;
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}
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static int uniphier_emmc_switch_part(uintptr_t host_base, int part_num)
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{
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struct uniphier_mmc_cmd cmd = {0};
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cmd.cmdidx = MMC_CMD_SWITCH;
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cmd.resp_type = MMC_RSP_R1b;
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cmd.cmdarg = (EXT_CSD_PART_CONF << 16) | (part_num << 8) | (3 << 24);
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return uniphier_emmc_send_cmd(host_base, &cmd);
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}
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static int uniphier_emmc_check_device_size(uintptr_t host_base,
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bool *is_block_addressing)
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{
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struct uniphier_mmc_cmd cmd = {0};
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uint32_t csd40, csd72; /* CSD[71:40], CSD[103:72] */
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int ret;
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cmd.cmdidx = MMC_CMD_SEND_CSD;
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cmd.resp_type = MMC_RSP_R2;
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cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
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ret = uniphier_emmc_send_cmd(host_base, &cmd);
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if (ret)
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return ret;
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csd40 = mmio_read_32(host_base + SDHCI_RESPONSE + 4);
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csd72 = mmio_read_32(host_base + SDHCI_RESPONSE + 8);
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/* C_SIZE == 0xfff && C_SIZE_MULT == 0x7 ? */
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*is_block_addressing = !(~csd40 & 0xffc00380) && !(~csd72 & 0x3);
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return 0;
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}
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static int uniphier_emmc_load_image(uintptr_t host_base,
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uint32_t dev_addr,
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unsigned long load_addr,
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uint32_t block_cnt)
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{
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struct uniphier_mmc_cmd cmd = {0};
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uint8_t tmp;
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assert((load_addr >> 32) == 0);
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mmio_write_32(host_base + SDHCI_DMA_ADDRESS, load_addr);
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mmio_write_16(host_base + SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(7, 512));
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mmio_write_16(host_base + SDHCI_BLOCK_COUNT, block_cnt);
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tmp = mmio_read_8(host_base + SDHCI_HOST_CONTROL);
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tmp &= ~SDHCI_CTRL_DMA_MASK;
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tmp |= SDHCI_CTRL_SDMA;
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mmio_write_8(host_base + SDHCI_HOST_CONTROL, tmp);
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tmp = mmio_read_8(host_base + SDHCI_BLOCK_GAP_CONTROL);
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tmp &= ~1; /* clear Stop At Block Gap Request */
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mmio_write_8(host_base + SDHCI_BLOCK_GAP_CONTROL, tmp);
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cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
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cmd.resp_type = MMC_RSP_R1;
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cmd.cmdarg = dev_addr;
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cmd.is_data = 1;
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return uniphier_emmc_send_cmd(host_base, &cmd);
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}
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static size_t uniphier_emmc_read(int lba, uintptr_t buf, size_t size)
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{
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int ret;
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inv_dcache_range(buf, size);
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if (!uniphier_emmc_host.is_block_addressing)
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lba *= 512;
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ret = uniphier_emmc_load_image(uniphier_emmc_host.base,
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lba, buf, size / 512);
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inv_dcache_range(buf, size);
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return ret ? 0 : size;
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}
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static struct io_block_dev_spec uniphier_emmc_dev_spec = {
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.ops = {
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.read = uniphier_emmc_read,
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},
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.block_size = 512,
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};
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static int uniphier_emmc_hw_init(struct uniphier_emmc_host *host)
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{
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struct uniphier_mmc_cmd cmd = {0};
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uintptr_t host_base = uniphier_emmc_host.base;
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int ret;
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/*
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* deselect card before SEND_CSD command.
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* Do not check the return code. It fails, but it is OK.
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*/
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cmd.cmdidx = MMC_CMD_SELECT_CARD;
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cmd.resp_type = MMC_RSP_R1;
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uniphier_emmc_send_cmd(host_base, &cmd); /* CMD7 (arg=0) */
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/* reset CMD Line */
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mmio_write_8(host_base + SDHCI_SOFTWARE_RESET,
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SDHCI_RESET_CMD | SDHCI_RESET_DATA);
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while (mmio_read_8(host_base + SDHCI_SOFTWARE_RESET))
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;
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ret = uniphier_emmc_check_device_size(host_base,
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&uniphier_emmc_host.is_block_addressing);
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if (ret)
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return ret;
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cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
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/* select card again */
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ret = uniphier_emmc_send_cmd(host_base, &cmd);
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if (ret)
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return ret;
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/* switch to Boot Partition 1 */
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ret = uniphier_emmc_switch_part(host_base, 1);
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if (ret)
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return ret;
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return 0;
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}
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static const uintptr_t uniphier_emmc_base[] = {
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[UNIPHIER_SOC_LD11] = 0x5a000200,
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[UNIPHIER_SOC_LD20] = 0x5a000200,
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[UNIPHIER_SOC_PXS3] = 0x5a000200,
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};
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int uniphier_emmc_init(unsigned int soc,
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struct io_block_dev_spec **block_dev_spec)
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{
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int ret;
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assert(soc < ARRAY_SIZE(uniphier_emmc_base));
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uniphier_emmc_host.base = uniphier_emmc_base[soc];
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if (uniphier_emmc_host.base == 0UL)
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return -ENOTSUP;
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ret = uniphier_emmc_hw_init(&uniphier_emmc_host);
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if (ret)
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return ret;
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*block_dev_spec = &uniphier_emmc_dev_spec;
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return 0;
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}
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