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117 lines
3.0 KiB
117 lines
3.0 KiB
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <drivers/arm/gicv3.h>
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#include <common/interrupt_props.h>
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#include <plat/common/platform.h>
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#include "uniphier.h"
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static uintptr_t uniphier_rdistif_base_addrs[PLATFORM_CORE_COUNT];
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static const interrupt_prop_t uniphier_interrupt_props[] = {
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/* G0 interrupts */
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/* SGI0 */
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INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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/* SGI6 */
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INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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/* G1S interrupts */
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/* Timer */
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INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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GIC_INTR_CFG_LEVEL),
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/* SGI1 */
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INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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GIC_INTR_CFG_EDGE),
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/* SGI2 */
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INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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GIC_INTR_CFG_EDGE),
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/* SGI3 */
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INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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GIC_INTR_CFG_EDGE),
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/* SGI4 */
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INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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GIC_INTR_CFG_EDGE),
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/* SGI5 */
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INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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GIC_INTR_CFG_EDGE),
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/* SGI7 */
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INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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GIC_INTR_CFG_EDGE)
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};
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static unsigned int uniphier_mpidr_to_core_pos(u_register_t mpidr)
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{
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return plat_core_pos_by_mpidr(mpidr);
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}
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static const struct gicv3_driver_data uniphier_gic_driver_data[] = {
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[UNIPHIER_SOC_LD11] = {
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.gicd_base = 0x5fe00000,
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.gicr_base = 0x5fe40000,
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.interrupt_props = uniphier_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props),
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = uniphier_rdistif_base_addrs,
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.mpidr_to_core_pos = uniphier_mpidr_to_core_pos,
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},
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[UNIPHIER_SOC_LD20] = {
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.gicd_base = 0x5fe00000,
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.gicr_base = 0x5fe80000,
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.interrupt_props = uniphier_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props),
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = uniphier_rdistif_base_addrs,
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.mpidr_to_core_pos = uniphier_mpidr_to_core_pos,
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},
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[UNIPHIER_SOC_PXS3] = {
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.gicd_base = 0x5fe00000,
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.gicr_base = 0x5fe80000,
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.interrupt_props = uniphier_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props),
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = uniphier_rdistif_base_addrs,
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.mpidr_to_core_pos = uniphier_mpidr_to_core_pos,
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},
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};
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void uniphier_gic_driver_init(unsigned int soc)
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{
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assert(soc < ARRAY_SIZE(uniphier_gic_driver_data));
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gicv3_driver_init(&uniphier_gic_driver_data[soc]);
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}
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void uniphier_gic_init(void)
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{
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void uniphier_gic_cpuif_enable(void)
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{
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void uniphier_gic_cpuif_disable(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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}
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void uniphier_gic_pcpu_init(void)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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}
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