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501 lines
13 KiB
501 lines
13 KiB
//===------ SparcDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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#ifdef CAPSTONE_HAS_SPARC
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#include <stdio.h> // DEBUG
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#include <stdlib.h>
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#include <string.h>
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#include "../../cs_priv.h"
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#include "../../utils.h"
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#include "SparcDisassembler.h"
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#include "../../MCInst.h"
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#include "../../MCInstrDesc.h"
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#include "../../MCFixedLenDisassembler.h"
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#include "../../MCRegisterInfo.h"
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#include "../../MCDisassembler.h"
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#include "../../MathExtras.h"
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#define GET_REGINFO_MC_DESC
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#define GET_REGINFO_ENUM
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#include "SparcGenRegisterInfo.inc"
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static const unsigned IntRegDecoderTable[] = {
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SP_G0, SP_G1, SP_G2, SP_G3,
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SP_G4, SP_G5, SP_G6, SP_G7,
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SP_O0, SP_O1, SP_O2, SP_O3,
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SP_O4, SP_O5, SP_O6, SP_O7,
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SP_L0, SP_L1, SP_L2, SP_L3,
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SP_L4, SP_L5, SP_L6, SP_L7,
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SP_I0, SP_I1, SP_I2, SP_I3,
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SP_I4, SP_I5, SP_I6, SP_I7
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};
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static const unsigned FPRegDecoderTable[] = {
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SP_F0, SP_F1, SP_F2, SP_F3,
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SP_F4, SP_F5, SP_F6, SP_F7,
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SP_F8, SP_F9, SP_F10, SP_F11,
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SP_F12, SP_F13, SP_F14, SP_F15,
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SP_F16, SP_F17, SP_F18, SP_F19,
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SP_F20, SP_F21, SP_F22, SP_F23,
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SP_F24, SP_F25, SP_F26, SP_F27,
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SP_F28, SP_F29, SP_F30, SP_F31
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};
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static const unsigned DFPRegDecoderTable[] = {
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SP_D0, SP_D16, SP_D1, SP_D17,
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SP_D2, SP_D18, SP_D3, SP_D19,
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SP_D4, SP_D20, SP_D5, SP_D21,
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SP_D6, SP_D22, SP_D7, SP_D23,
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SP_D8, SP_D24, SP_D9, SP_D25,
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SP_D10, SP_D26, SP_D11, SP_D27,
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SP_D12, SP_D28, SP_D13, SP_D29,
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SP_D14, SP_D30, SP_D15, SP_D31
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};
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static const unsigned QFPRegDecoderTable[] = {
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SP_Q0, SP_Q8, ~0U, ~0U,
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SP_Q1, SP_Q9, ~0U, ~0U,
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SP_Q2, SP_Q10, ~0U, ~0U,
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SP_Q3, SP_Q11, ~0U, ~0U,
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SP_Q4, SP_Q12, ~0U, ~0U,
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SP_Q5, SP_Q13, ~0U, ~0U,
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SP_Q6, SP_Q14, ~0U, ~0U,
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SP_Q7, SP_Q15, ~0U, ~0U
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};
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static const unsigned FCCRegDecoderTable[] = {
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SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3
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};
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static uint64_t getFeatureBits(int mode)
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{
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// support everything
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return (uint64_t)-1;
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}
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static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder)
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{
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unsigned Reg;
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if (RegNo > 31)
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return MCDisassembler_Fail;
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Reg = IntRegDecoderTable[RegNo];
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder)
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{
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unsigned Reg;
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if (RegNo > 31)
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return MCDisassembler_Fail;
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Reg = IntRegDecoderTable[RegNo];
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder)
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{
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unsigned Reg;
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if (RegNo > 31)
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return MCDisassembler_Fail;
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Reg = FPRegDecoderTable[RegNo];
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder)
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{
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unsigned Reg;
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if (RegNo > 31)
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return MCDisassembler_Fail;
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Reg = DFPRegDecoderTable[RegNo];
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder)
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{
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unsigned Reg;
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if (RegNo > 31)
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return MCDisassembler_Fail;
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Reg = QFPRegDecoderTable[RegNo];
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if (Reg == ~0U)
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return MCDisassembler_Fail;
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder)
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{
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if (RegNo > 3)
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return MCDisassembler_Fail;
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MCOperand_CreateReg0(Inst, FCCRegDecoderTable[RegNo]);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeCall(MCInst *Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSIMM13(MCInst *Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeJMPL(MCInst *Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSWAP(MCInst *Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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#define GET_SUBTARGETINFO_ENUM
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#include "SparcGenSubtargetInfo.inc"
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#include "SparcGenDisassemblerTables.inc"
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/// readInstruction - read four bytes and return 32 bit word.
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static DecodeStatus readInstruction32(const uint8_t *code, size_t len, uint32_t *Insn)
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{
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if (len < 4)
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// not enough data
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return MCDisassembler_Fail;
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// Encoded as a big-endian 32-bit word in the stream.
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*Insn = (code[3] << 0) |
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(code[2] << 8) |
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(code[1] << 16) |
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((uint32_t) code[0] << 24);
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return MCDisassembler_Success;
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}
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bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,
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uint16_t *size, uint64_t address, void *info)
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{
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uint32_t Insn;
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DecodeStatus Result;
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Result = readInstruction32(code, code_len, &Insn);
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if (Result == MCDisassembler_Fail)
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return false;
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if (MI->flat_insn->detail) {
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memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sparc)+sizeof(cs_sparc));
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}
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Result = decodeInstruction_4(DecoderTableSparc32, MI, Insn, address,
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(MCRegisterInfo *)info, 0);
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if (Result != MCDisassembler_Fail) {
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*size = 4;
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return true;
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}
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return false;
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}
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typedef DecodeStatus (*DecodeFunc)(MCInst *MI, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMem(MCInst *MI, unsigned insn, uint64_t Address,
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const void *Decoder,
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bool isLoad, DecodeFunc DecodeRD)
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{
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DecodeStatus status;
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unsigned rd = fieldFromInstruction_4(insn, 25, 5);
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unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
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bool isImm = fieldFromInstruction_4(insn, 13, 1) != 0;
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unsigned rs2 = 0;
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unsigned simm13 = 0;
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if (isImm)
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simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
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else
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rs2 = fieldFromInstruction_4(insn, 0, 5);
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if (isLoad) {
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status = DecodeRD(MI, rd, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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}
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// Decode rs1.
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status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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// Decode imm|rs2.
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if (isImm)
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MCOperand_CreateImm0(MI, simm13);
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else {
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status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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}
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if (!isLoad) {
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status = DecodeRD(MI, rd, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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}
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address,
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const void *Decoder)
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{
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return DecodeMem(Inst, insn, Address, Decoder, true,
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DecodeIntRegsRegisterClass);
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}
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static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address,
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const void *Decoder)
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{
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return DecodeMem(Inst, insn, Address, Decoder, true,
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DecodeFPRegsRegisterClass);
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}
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static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address,
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const void *Decoder)
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{
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return DecodeMem(Inst, insn, Address, Decoder, true,
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DecodeDFPRegsRegisterClass);
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}
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static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address,
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const void *Decoder)
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{
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return DecodeMem(Inst, insn, Address, Decoder, true,
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DecodeQFPRegsRegisterClass);
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}
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static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn,
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uint64_t Address, const void *Decoder)
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{
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return DecodeMem(Inst, insn, Address, Decoder, false,
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DecodeIntRegsRegisterClass);
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}
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static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, uint64_t Address,
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const void *Decoder)
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{
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return DecodeMem(Inst, insn, Address, Decoder, false,
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DecodeFPRegsRegisterClass);
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}
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static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn,
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uint64_t Address, const void *Decoder)
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{
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return DecodeMem(Inst, insn, Address, Decoder, false,
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DecodeDFPRegsRegisterClass);
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}
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static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn,
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uint64_t Address, const void *Decoder)
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{
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return DecodeMem(Inst, insn, Address, Decoder, false,
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DecodeQFPRegsRegisterClass);
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}
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static DecodeStatus DecodeCall(MCInst *MI, unsigned insn,
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uint64_t Address, const void *Decoder)
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{
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unsigned tgt = fieldFromInstruction_4(insn, 0, 30);
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tgt <<= 2;
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MCOperand_CreateImm0(MI, tgt);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSIMM13(MCInst *MI, unsigned insn,
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uint64_t Address, const void *Decoder)
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{
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unsigned tgt = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
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MCOperand_CreateImm0(MI, tgt);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeJMPL(MCInst *MI, unsigned insn, uint64_t Address,
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const void *Decoder)
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{
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DecodeStatus status;
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unsigned rd = fieldFromInstruction_4(insn, 25, 5);
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unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
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unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
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unsigned rs2 = 0;
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unsigned simm13 = 0;
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if (isImm)
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simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
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else
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rs2 = fieldFromInstruction_4(insn, 0, 5);
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// Decode RD.
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status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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// Decode RS1.
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status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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// Decode RS1 | SIMM13.
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if (isImm)
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MCOperand_CreateImm0(MI, simm13);
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else {
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status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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}
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address,
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const void *Decoder)
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{
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DecodeStatus status;
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unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
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unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
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unsigned rs2 = 0;
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unsigned simm13 = 0;
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if (isImm)
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simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
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else
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rs2 = fieldFromInstruction_4(insn, 0, 5);
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// Decode RS1.
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status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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// Decode RS2 | SIMM13.
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if (isImm)
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MCOperand_CreateImm0(MI, simm13);
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else {
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status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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}
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSWAP(MCInst *MI, unsigned insn, uint64_t Address,
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const void *Decoder)
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{
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DecodeStatus status;
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unsigned rd = fieldFromInstruction_4(insn, 25, 5);
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unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
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unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
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unsigned rs2 = 0;
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unsigned simm13 = 0;
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if (isImm)
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simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
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else
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rs2 = fieldFromInstruction_4(insn, 0, 5);
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// Decode RD.
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status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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// Decode RS1.
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status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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// Decode RS1 | SIMM13.
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if (isImm)
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MCOperand_CreateImm0(MI, simm13);
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else {
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status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
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if (status != MCDisassembler_Success)
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return status;
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}
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return MCDisassembler_Success;
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}
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void Sparc_init(MCRegisterInfo *MRI)
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{
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/*
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InitMCRegisterInfo(SparcRegDesc, 119, RA, PC,
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SparcMCRegisterClasses, 8,
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SparcRegUnitRoots,
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86,
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SparcRegDiffLists,
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SparcRegStrings,
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SparcSubRegIdxLists,
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7,
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SparcSubRegIdxRanges,
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SparcRegEncodingTable);
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*/
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MCRegisterInfo_InitMCRegisterInfo(MRI, SparcRegDesc, 119,
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0, 0,
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SparcMCRegisterClasses, 8,
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0, 0,
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SparcRegDiffLists,
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0,
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SparcSubRegIdxLists, 7,
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0);
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}
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#endif
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