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363 lines
9.6 KiB
363 lines
9.6 KiB
/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/** @file gen8_instruction.h
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*
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* A representation of a Gen8+ EU instruction, with helper methods to get
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* and set various fields. This is the actual hardware format.
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*/
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#ifndef GEN8_INSTRUCTION_H
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#define GEN8_INSTRUCTION_H
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#include <stdio.h>
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#include <stdint.h>
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#include "brw_compat.h"
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#include "brw_reg.h"
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struct gen8_instruction {
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uint32_t data[4];
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};
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static inline unsigned gen8_bits(struct gen8_instruction *insn,
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unsigned high,
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unsigned low);
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static inline void gen8_set_bits(struct gen8_instruction *insn,
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unsigned high,
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unsigned low,
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unsigned value);
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#define F(name, high, low) \
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static inline void gen8_set_##name(struct gen8_instruction *insn, unsigned v) \
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{ \
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gen8_set_bits(insn, high, low, v); \
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} \
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static inline unsigned gen8_##name(struct gen8_instruction *insn) \
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{ \
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return gen8_bits(insn, high, low); \
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}
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/**
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* Direct addressing only:
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* @{
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*/
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F(src1_da_reg_nr, 108, 101);
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F(src0_da_reg_nr, 76, 69);
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F(dst_da1_hstride, 62, 61);
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F(dst_da_reg_nr, 60, 53);
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F(dst_da16_subreg_nr, 52, 52);
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F(dst_da1_subreg_nr, 52, 48);
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F(da16_writemask, 51, 48); /* Dst.ChanEn */
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/** @} */
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F(src1_vert_stride, 120, 117)
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F(src1_da1_width, 116, 114)
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F(src1_da16_swiz_w, 115, 114)
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F(src1_da16_swiz_z, 113, 112)
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F(src1_da1_hstride, 113, 112)
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F(src1_address_mode, 111, 111)
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/** Src1.SrcMod @{ */
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F(src1_negate, 110, 110)
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F(src1_abs, 109, 109)
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/** @} */
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F(src1_da16_subreg_nr, 100, 100)
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F(src1_da1_subreg_nr, 100, 96)
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F(src1_da16_swiz_y, 99, 98)
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F(src1_da16_swiz_x, 97, 96)
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F(src1_reg_type, 94, 91)
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F(src1_reg_file, 90, 89)
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F(src0_vert_stride, 88, 85)
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F(src0_da1_width, 84, 82)
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F(src0_da16_swiz_w, 83, 82)
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F(src0_da16_swiz_z, 81, 80)
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F(src0_da1_hstride, 81, 80)
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F(src0_address_mode, 79, 79)
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/** Src0.SrcMod @{ */
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F(src0_negate, 78, 78)
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F(src0_abs, 77, 77)
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/** @} */
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F(src0_da16_subreg_nr, 68, 68)
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F(src0_da1_subreg_nr, 68, 64)
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F(src0_da16_swiz_y, 67, 66)
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F(src0_da16_swiz_x, 65, 64)
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F(dst_address_mode, 63, 63)
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F(src0_reg_type, 46, 43)
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F(src0_reg_file, 42, 41)
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F(dst_reg_type, 40, 37)
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F(dst_reg_file, 36, 35)
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F(mask_control, 34, 34)
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F(flag_reg_nr, 33, 33)
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F(flag_subreg_nr, 32, 32)
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F(saturate, 31, 31)
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F(branch_control, 30, 30)
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F(debug_control, 30, 30)
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F(cmpt_control, 29, 29)
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F(acc_wr_control, 28, 28)
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F(cond_modifier, 27, 24)
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F(exec_size, 23, 21)
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F(pred_inv, 20, 20)
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F(pred_control, 19, 16)
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F(thread_control, 15, 14)
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F(qtr_control, 13, 12)
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F(nib_control, 11, 11)
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F(dep_control, 10, 9)
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F(access_mode, 8, 8)
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/* Bit 7 is Reserve d (for future Opcode expansion) */
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F(opcode, 6, 0)
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/**
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* Three-source instructions:
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* @{
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*/
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F(src2_3src_reg_nr, 125, 118)
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F(src2_3src_subreg_nr, 117, 115)
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F(src2_3src_swizzle, 114, 107)
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F(src2_3src_rep_ctrl, 106, 106)
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F(src1_3src_reg_nr, 104, 97)
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F(src1_3src_subreg_hi, 96, 96)
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F(src1_3src_subreg_lo, 95, 94)
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F(src1_3src_swizzle, 93, 86)
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F(src1_3src_rep_ctrl, 85, 85)
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F(src0_3src_reg_nr, 83, 76)
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F(src0_3src_subreg_nr, 75, 73)
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F(src0_3src_swizzle, 72, 65)
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F(src0_3src_rep_ctrl, 64, 64)
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F(dst_3src_reg_nr, 63, 56)
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F(dst_3src_subreg_nr, 55, 53)
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F(dst_3src_writemask, 52, 49)
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F(dst_3src_type, 48, 46)
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F(src_3src_type, 45, 43)
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F(src2_3src_negate, 42, 42)
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F(src2_3src_abs, 41, 41)
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F(src1_3src_negate, 40, 40)
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F(src1_3src_abs, 39, 39)
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F(src0_3src_negate, 38, 38)
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F(src0_3src_abs, 37, 37)
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/** @} */
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/**
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* Fields for SEND messages:
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* @{
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*/
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F(eot, 127, 127)
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F(mlen, 124, 121)
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F(rlen, 120, 116)
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F(header_present, 115, 115)
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F(function_control, 114, 96)
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F(sfid, 27, 24)
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F(math_function, 27, 24)
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/** @} */
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/**
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* URB message function control bits:
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* @{
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*/
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F(urb_per_slot_offset, 113, 113)
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F(urb_interleave, 111, 111)
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F(urb_global_offset, 110, 100)
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F(urb_opcode, 99, 96)
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/** @} */
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/**
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* Sampler message function control bits:
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* @{
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*/
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F(sampler_simd_mode, 114, 113)
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F(sampler_msg_type, 112, 108)
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F(sampler, 107, 104)
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F(binding_table_index, 103, 96)
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/** @} */
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/**
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* Data port message function control bits:
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* @ {
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*/
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F(dp_category, 114, 114)
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F(dp_message_type, 113, 110)
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F(dp_message_control, 109, 104)
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F(dp_binding_table_index, 103, 96)
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/** @} */
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/**
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* Thread Spawn message function control bits:
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* @ {
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*/
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F(ts_resource_select, 100, 100)
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F(ts_request_type, 97, 97)
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F(ts_opcode, 96, 96)
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/** @} */
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/**
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* Video Motion Estimation message function control bits:
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* @ {
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*/
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F(vme_message_type, 110, 109)
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F(vme_binding_table_index, 103, 96)
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/** @} */
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/**
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* Check & Refinement Engine message function control bits:
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* @ {
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*/
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F(cre_message_type, 110, 109)
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F(cre_binding_table_index, 103, 96)
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/** @} */
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/* Addr Mode */
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F(dst_addr_mode, 63, 63)
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F(src0_addr_mode, 79, 79)
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F(src1_addr_mode, 111, 111)
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/* Indirect access mode for Align1. */
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F(dst_ida1_sub_nr, 60, 57)
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F(src0_ida1_sub_nr, 76, 73)
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F(src1_ida1_sub_nr, 108, 105)
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/* Imm[8:0] of Immediate addr offset under Indirect mode */
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F(dst_ida1_imm8, 56, 48)
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F(src0_ida1_imm8, 72, 64)
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F(src1_ida1_imm8, 104, 96)
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/* Imm Bit9 of Immediate addr offset under Indirect mode */
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F(dst_ida1_imm9, 47, 47)
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F(src0_ida1_imm9, 95, 95)
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F(src1_ida1_imm9, 121, 121)
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#undef F
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#define IMM8_MASK 0x1FF
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#define IMM9_MASK 0x200
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/**
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* Flow control instruction bits:
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* @{
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*/
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static inline unsigned gen8_uip(struct gen8_instruction *insn)
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{
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return insn->data[2];
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}
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static inline void gen8_set_uip(struct gen8_instruction *insn, unsigned uip)
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{
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insn->data[2] = uip;
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}
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static inline unsigned gen8_jip(struct gen8_instruction *insn)
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{
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return insn->data[3];
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}
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static inline void gen8_set_jip(struct gen8_instruction *insn, unsigned jip)
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{
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insn->data[3] = jip;
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}
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/** @} */
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static inline int gen8_src1_imm_d(struct gen8_instruction *insn)
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{
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return insn->data[3];
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}
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static inline unsigned gen8_src1_imm_ud(struct gen8_instruction *insn)
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{
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return insn->data[3];
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}
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static inline float gen8_src1_imm_f(struct gen8_instruction *insn)
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{
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fi_type ft;
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ft.u = insn->data[3];
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return ft.f;
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}
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void gen8_set_dst(struct gen8_instruction *insn, struct brw_reg reg);
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void gen8_set_src0(struct gen8_instruction *insn, struct brw_reg reg);
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void gen8_set_src1(struct gen8_instruction *insn, struct brw_reg reg);
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void gen8_set_urb_message(struct gen8_instruction *insn,
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unsigned opcode, unsigned mlen, unsigned rlen,
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bool eot, unsigned offset, bool interleave);
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void gen8_set_sampler_message(struct gen8_instruction *insn,
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unsigned binding_table_index, unsigned sampler,
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unsigned msg_type, unsigned rlen, unsigned mlen,
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bool header_present, unsigned simd_mode);
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void gen8_set_dp_message(struct gen8_instruction *insn,
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enum brw_message_target sfid,
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unsigned binding_table_index,
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unsigned msg_type,
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unsigned msg_control,
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unsigned msg_length,
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unsigned response_length,
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bool header_present,
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bool end_of_thread);
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/** Disassemble the instruction. */
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int gen8_disassemble(FILE *file, struct gen8_instruction *insn, int gen);
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/**
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* Fetch a set of contiguous bits from the instruction.
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*
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* Bits indexes range from 0..127; fields may not cross 32-bit boundaries.
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*/
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static inline unsigned
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gen8_bits(struct gen8_instruction *insn, unsigned high, unsigned low)
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{
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/* We assume the field doesn't cross 32-bit boundaries. */
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const unsigned word = high / 32;
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assert(word == low / 32);
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high %= 32;
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low %= 32;
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const unsigned mask = (((1 << (high - low + 1)) - 1) << low);
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return (insn->data[word] & mask) >> low;
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}
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/**
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* Set bits in the instruction, with proper shifting and masking.
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*
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* Bits indexes range from 0..127; fields may not cross 32-bit boundaries.
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*/
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static inline void
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gen8_set_bits(struct gen8_instruction *insn,
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unsigned high,
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unsigned low,
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unsigned value)
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{
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const unsigned word = high / 32;
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assert(word == low / 32);
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high %= 32;
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low %= 32;
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const unsigned mask = (((1 << (high - low + 1)) - 1) << low);
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insn->data[word] = (insn->data[word] & ~mask) | ((value << low) & mask);
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}
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void gen9_set_send_extdesc(struct gen8_instruction *insn, unsigned int value);
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#endif
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