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406 lines
9.8 KiB
406 lines
9.8 KiB
/*
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* Copyright © 2011 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Chris Wilson <chris@chris-wilson.co.uk>
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*
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*/
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#include <unistd.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/poll.h>
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#include <sys/ioctl.h>
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#include <sys/time.h>
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#include <time.h>
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#include "drm.h"
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#include "ioctl_wrappers.h"
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#include "drmtest.h"
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#include "intel_chipset.h"
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#include "intel_reg.h"
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#include "igt_stats.h"
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#include "i915/gem_mman.h"
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#define LOCAL_I915_EXEC_NO_RELOC (1<<11)
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#define LOCAL_I915_EXEC_HANDLE_LUT (1<<12)
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#define LOCAL_I915_EXEC_BSD_SHIFT (13)
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#define LOCAL_I915_EXEC_BSD_MASK (3 << LOCAL_I915_EXEC_BSD_SHIFT)
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#define ENGINE_FLAGS (I915_EXEC_RING_MASK | LOCAL_I915_EXEC_BSD_MASK)
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#define WRITE 0x1
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#define IDLE 0x2
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#define DMABUF 0x4
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#define WAIT 0x8
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#define SYNC 0x10
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#define SYNCOBJ 0x20
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#define LOCAL_I915_EXEC_FENCE_ARRAY (1 << 19)
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struct local_gem_exec_fence {
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uint32_t handle;
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uint32_t flags;
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#define LOCAL_EXEC_FENCE_WAIT (1 << 0)
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#define LOCAL_EXEC_FENCE_SIGNAL (1 << 1)
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};
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static void gem_busy(int fd, uint32_t handle)
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{
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struct drm_i915_gem_busy busy = { .handle = handle };
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ioctl(fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
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}
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static void gem_wait__busy(int fd, uint32_t handle)
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{
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struct drm_i915_gem_wait wait = { .bo_handle = handle };
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ioctl(fd, DRM_IOCTL_I915_GEM_WAIT, &wait);
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}
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static double elapsed(const struct timespec *start,
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const struct timespec *end)
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{
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return 1e9*(end->tv_sec - start->tv_sec) +
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(end->tv_nsec - start->tv_nsec);
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}
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struct sync_merge_data {
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char name[32];
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__s32 fd2;
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__s32 fence;
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__u32 flags;
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__u32 pad;
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};
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#define SYNC_IOC_MAGIC '>'
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#define SYNC_IOC_MERGE _IOWR(SYNC_IOC_MAGIC, 3, struct sync_merge_data)
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static int sync_merge(int fd1, int fd2)
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{
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struct sync_merge_data data;
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if (fd1 == -1)
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return dup(fd2);
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if (fd2 == -1)
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return dup(fd1);
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memset(&data, 0, sizeof(data));
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data.fd2 = fd2;
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strcpy(data.name, "i965");
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if (ioctl(fd1, SYNC_IOC_MERGE, &data))
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return -errno;
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return data.fence;
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}
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static uint32_t __syncobj_create(int fd)
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{
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struct local_syncobj_create {
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uint32_t handle, flags;
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} arg;
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#define LOCAL_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct local_syncobj_create)
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memset(&arg, 0, sizeof(arg));
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ioctl(fd, LOCAL_IOCTL_SYNCOBJ_CREATE, &arg);
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return arg.handle;
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}
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static uint32_t syncobj_create(int fd)
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{
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uint32_t ret;
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igt_assert_neq((ret = __syncobj_create(fd)), 0);
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return ret;
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}
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#define LOCAL_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
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#define LOCAL_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
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struct local_syncobj_wait {
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__u64 handles;
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/* absolute timeout */
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__s64 timeout_nsec;
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__u32 count_handles;
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__u32 flags;
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__u32 first_signaled; /* only valid when not waiting all */
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__u32 pad;
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};
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#define LOCAL_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct local_syncobj_wait)
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static int __syncobj_wait(int fd, struct local_syncobj_wait *args)
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{
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int err = 0;
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if (drmIoctl(fd, LOCAL_IOCTL_SYNCOBJ_WAIT, args))
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err = -errno;
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return err;
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}
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static int loop(unsigned ring, int reps, int ncpus, unsigned flags)
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{
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_exec_object2 obj[2];
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struct drm_i915_gem_relocation_entry reloc[2];
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struct local_gem_exec_fence syncobj;
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unsigned engines[16];
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unsigned nengine;
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uint32_t *batch;
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double *shared;
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int fd, i, gen;
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int dmabuf;
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shared = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
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fd = drm_open_driver(DRIVER_INTEL);
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gen = intel_gen(intel_get_drm_devid(fd));
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memset(obj, 0, sizeof(obj));
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obj[0].handle = gem_create(fd, 4096);
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if (flags & WRITE)
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obj[0].flags = EXEC_OBJECT_WRITE;
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obj[1].handle = gem_create(fd, 4096);
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if (gem_mmap__has_wc(fd))
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batch = gem_mmap__wc(fd, obj[1].handle, 0, 4096, PROT_WRITE);
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else
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batch = gem_mmap__gtt(fd, obj[1].handle, 4096, PROT_WRITE);
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gem_set_domain(fd, obj[1].handle,
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I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
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batch[0] = MI_BATCH_BUFFER_END;
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffers_ptr = to_user_pointer(obj);
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execbuf.buffer_count = 2;
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execbuf.flags |= LOCAL_I915_EXEC_HANDLE_LUT;
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execbuf.flags |= LOCAL_I915_EXEC_NO_RELOC;
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if (__gem_execbuf(fd, &execbuf)) {
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execbuf.flags = 0;
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if (__gem_execbuf(fd, &execbuf))
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return 77;
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}
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if (flags & SYNCOBJ) {
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syncobj.handle = syncobj_create(fd);
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syncobj.flags = LOCAL_EXEC_FENCE_SIGNAL;
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execbuf.cliprects_ptr = to_user_pointer(&syncobj);
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execbuf.num_cliprects = 1;
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execbuf.flags |= LOCAL_I915_EXEC_FENCE_ARRAY;
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}
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if (ring == -1) {
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nengine = 0;
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for (ring = 1; ring < 16; ring++) {
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execbuf.flags &= ~ENGINE_FLAGS;
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execbuf.flags |= ring;
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if (__gem_execbuf(fd, &execbuf) == 0)
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engines[nengine++] = ring;
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}
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} else {
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nengine = 1;
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engines[0] = ring;
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}
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obj[1].relocs_ptr = to_user_pointer(reloc);
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obj[1].relocation_count = 2;
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if (flags & DMABUF)
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dmabuf = prime_handle_to_fd(fd, obj[0].handle);
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gem_set_domain(fd, obj[1].handle,
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I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
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reloc[0].target_handle = obj[1].handle; /* recurse */
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reloc[0].presumed_offset = obj[1].offset;
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reloc[0].offset = sizeof(uint32_t);
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reloc[0].delta = 0;
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if (gen < 4)
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reloc[0].delta = 1;
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reloc[0].read_domains = I915_GEM_DOMAIN_COMMAND;
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reloc[0].write_domain = 0;
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reloc[1].target_handle = obj[0].handle;
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reloc[1].presumed_offset = obj[0].offset;
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reloc[1].offset = 1024;
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reloc[1].delta = 0;
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reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
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reloc[1].write_domain = 0;
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if (flags & WRITE)
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reloc[1].write_domain = I915_GEM_DOMAIN_RENDER;
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while (reps--) {
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int fence = -1;
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memset(shared, 0, 4096);
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gem_set_domain(fd, obj[1].handle,
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I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
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sleep(1); /* wait for the hw to go back to sleep */
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batch[i = 0] = MI_BATCH_BUFFER_START;
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if (gen >= 8) {
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batch[i] |= 1 << 8 | 1;
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batch[++i] = obj[1].offset;
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batch[++i] = obj[1].offset >> 32;
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} else if (gen >= 6) {
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batch[i] |= 1 << 8;
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batch[++i] = obj[1].offset;
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} else {
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batch[i] |= 2 << 6;
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batch[++i] = obj[1].offset;
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if (gen < 4)
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batch[i] |= 1;
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}
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if ((flags & IDLE) == 0) {
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for (int n = 0; n < nengine; n++) {
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execbuf.flags &= ~(3 << 16);
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if (flags & SYNC)
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execbuf.flags |= 1 << 17;
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execbuf.flags &= ~ENGINE_FLAGS;
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execbuf.flags |= engines[n];
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gem_execbuf_wr(fd, &execbuf);
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if (execbuf.flags & (1 << 17))
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fence = sync_merge(fence, execbuf.rsvd2 >> 32);
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}
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}
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igt_fork(child, ncpus) {
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struct timespec start, end;
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unsigned count = 0;
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clock_gettime(CLOCK_MONOTONIC, &start);
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do {
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if (flags & DMABUF) {
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struct pollfd pfd = { .fd = dmabuf, .events = POLLOUT };
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for (int inner = 0; inner < 1024; inner++)
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poll(&pfd, 1, 0);
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} else if (flags & SYNCOBJ) {
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struct local_syncobj_wait arg = {
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.handles = to_user_pointer(&syncobj.handle),
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.count_handles = 1,
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};
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for (int inner = 0; inner < 1024; inner++)
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__syncobj_wait(fd, &arg);
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} else if (flags & SYNC) {
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struct pollfd pfd = { .fd = fence, .events = POLLOUT };
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for (int inner = 0; inner < 1024; inner++)
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poll(&pfd, 1, 0);
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} else if (flags & WAIT) {
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for (int inner = 0; inner < 1024; inner++)
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gem_wait__busy(fd, obj[0].handle);
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} else {
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for (int inner = 0; inner < 1024; inner++)
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gem_busy(fd, obj[0].handle);
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}
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clock_gettime(CLOCK_MONOTONIC, &end);
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count += 1024;
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} while (elapsed(&start, &end) < 2e9);
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clock_gettime(CLOCK_MONOTONIC, &end);
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shared[child] = elapsed(&start, &end) / count;
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}
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igt_waitchildren();
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batch[0] = MI_BATCH_BUFFER_END;
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if (fence != -1)
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close(fence);
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for (int child = 0; child < ncpus; child++)
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shared[ncpus] += shared[child];
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printf("%7.3f\n", shared[ncpus] / ncpus);
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}
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return 0;
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}
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int main(int argc, char **argv)
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{
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unsigned ring = I915_EXEC_RENDER;
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unsigned flags = 0;
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int reps = 1;
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int ncpus = 1;
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int c;
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while ((c = getopt (argc, argv, "e:r:dfsSwWI")) != -1) {
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switch (c) {
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case 'e':
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if (strcmp(optarg, "rcs") == 0)
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ring = I915_EXEC_RENDER;
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else if (strcmp(optarg, "vcs") == 0)
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ring = I915_EXEC_BSD;
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else if (strcmp(optarg, "bcs") == 0)
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ring = I915_EXEC_BLT;
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else if (strcmp(optarg, "vecs") == 0)
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ring = I915_EXEC_VEBOX;
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else if (strcmp(optarg, "all") == 0)
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ring = -1;
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else
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ring = atoi(optarg);
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break;
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case 'r':
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reps = atoi(optarg);
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if (reps < 1)
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reps = 1;
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break;
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case 'f':
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ncpus = sysconf(_SC_NPROCESSORS_ONLN);
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break;
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case 'd':
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flags |= DMABUF;
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break;
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case 'w':
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flags |= WAIT;
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break;
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case 's':
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flags |= SYNC;
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break;
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case 'S':
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flags |= SYNCOBJ;
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break;
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case 'W':
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flags |= WRITE;
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break;
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case 'I':
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flags |= IDLE;
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break;
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default:
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break;
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}
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}
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return loop(ring, reps, ncpus, flags);
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}
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