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323 lines
10 KiB
323 lines
10 KiB
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Tiago Vignatti
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*/
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/** @file prime_mmap_coherency.c
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*
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* TODO: need to show the need for prime_sync_end().
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*/
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#include "igt.h"
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IGT_TEST_DESCRIPTION("Test dma-buf mmap on !llc platforms mostly and provoke"
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" coherency bugs so we know for sure where we need the sync ioctls.");
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int fd;
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static drm_intel_bufmgr *bufmgr;
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struct intel_batchbuffer *batch;
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static int width = 1024, height = 1024;
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/*
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* Exercises the need for read flush:
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* 1. create a BO and write '0's, in GTT domain.
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* 2. read BO using the dma-buf CPU mmap.
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* 3. write '1's, in GTT domain.
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* 4. read again through the mapped dma-buf.
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*/
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static int test_read_flush(void)
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{
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drm_intel_bo *bo_1;
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drm_intel_bo *bo_2;
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uint32_t *ptr_cpu;
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uint32_t *ptr_gtt;
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int dma_buf_fd, i;
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int stale = 0;
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bo_1 = drm_intel_bo_alloc(bufmgr, "BO 1", width * height * 4, 4096);
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/* STEP #1: put the BO 1 in GTT domain. We use the blitter to copy and fill
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* zeros to BO 1, so commands will be submitted and likely to place BO 1 in
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* the GTT domain. */
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bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
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intel_copy_bo(batch, bo_1, bo_2, width * height);
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drm_intel_bo_unreference(bo_2);
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/* STEP #2: read BO 1 using the dma-buf CPU mmap. This dirties the CPU caches. */
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dma_buf_fd = prime_handle_to_fd_for_mmap(fd, bo_1->handle);
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/* STEP #3: write 0x11 into BO 1. */
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bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
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ptr_gtt = gem_mmap__gtt(fd, bo_2->handle, width * height, PROT_READ | PROT_WRITE);
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gem_set_domain(fd, bo_2->handle,
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I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
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memset(ptr_gtt, 0xc5, width * height);
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munmap(ptr_gtt, width * height);
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ptr_cpu = mmap(NULL, width * height, PROT_READ,
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MAP_SHARED, dma_buf_fd, 0);
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igt_assert(ptr_cpu != MAP_FAILED);
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prime_sync_start(dma_buf_fd, false);
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for (i = 0; i < (width * height) / 4; i++)
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igt_assert_eq(ptr_cpu[i], 0);
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prime_sync_end(dma_buf_fd, false);
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intel_copy_bo(batch, bo_1, bo_2, width * height);
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drm_intel_bo_unreference(bo_2);
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/* STEP #4: read again using the CPU mmap. Doing #1 before #3 makes sure we
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* don't do a full CPU cache flush in step #3 again. That makes sure all the
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* stale cachelines from step #2 survive (mostly, a few will be evicted)
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* until we try to read them again in step #4. This behavior could be fixed
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* by flush CPU read right before accessing the CPU pointer */
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prime_sync_start(dma_buf_fd, false);
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for (i = 0; i < (width * height) / 4; i++)
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if (ptr_cpu[i] != 0xc5c5c5c5)
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stale++;
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prime_sync_end(dma_buf_fd, false);
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drm_intel_bo_unreference(bo_1);
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munmap(ptr_cpu, width * height);
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close(dma_buf_fd);
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return stale;
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}
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/*
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* Exercises the need for write flush:
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* 1. create BO 1 and write '0's, in GTT domain.
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* 2. write '1's into BO 1 using the dma-buf CPU mmap.
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* 3. copy BO 1 to new BO 2, in GTT domain.
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* 4. read via dma-buf mmap BO 2.
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*/
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static int test_write_flush(void)
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{
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drm_intel_bo *bo_1;
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drm_intel_bo *bo_2;
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uint32_t *ptr_cpu;
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uint32_t *ptr2_cpu;
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int dma_buf_fd, dma_buf2_fd, i;
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int stale = 0;
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bo_1 = drm_intel_bo_alloc(bufmgr, "BO 1", width * height * 4, 4096);
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/* STEP #1: Put the BO 1 in GTT domain. We use the blitter to copy and fill
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* zeros to BO 1, so commands will be submitted and likely to place BO 1 in
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* the GTT domain. */
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bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
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intel_copy_bo(batch, bo_1, bo_2, width * height);
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drm_intel_bo_unreference(bo_2);
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/* STEP #2: Write '1's into BO 1 using the dma-buf CPU mmap. */
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dma_buf_fd = prime_handle_to_fd_for_mmap(fd, bo_1->handle);
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igt_skip_on(errno == EINVAL);
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ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
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MAP_SHARED, dma_buf_fd, 0);
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igt_assert(ptr_cpu != MAP_FAILED);
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/* This is the main point of this test: !llc hw requires a cache write
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* flush right here (explained in step #4). */
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prime_sync_start(dma_buf_fd, true);
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memset(ptr_cpu, 0x11, width * height);
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prime_sync_end(dma_buf_fd, true);
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/* STEP #3: Copy BO 1 into BO 2, using blitter. */
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bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096);
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intel_copy_bo(batch, bo_2, bo_1, width * height);
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/* STEP #4: compare BO 2 against written BO 1. In !llc hardware, there
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* should be some cache lines that didn't get flushed out and are still 0,
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* requiring cache flush before the write in step 2. */
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dma_buf2_fd = prime_handle_to_fd_for_mmap(fd, bo_2->handle);
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igt_skip_on(errno == EINVAL);
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ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
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MAP_SHARED, dma_buf2_fd, 0);
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igt_assert(ptr2_cpu != MAP_FAILED);
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prime_sync_start(dma_buf2_fd, false);
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for (i = 0; i < (width * height) / 4; i++)
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if (ptr2_cpu[i] != 0x11111111)
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stale++;
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prime_sync_end(dma_buf2_fd, false);
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drm_intel_bo_unreference(bo_1);
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drm_intel_bo_unreference(bo_2);
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munmap(ptr_cpu, width * height);
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close(dma_buf2_fd);
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close(dma_buf_fd);
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return stale;
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}
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static void blit_and_cmp(void)
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{
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drm_intel_bo *bo_1;
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drm_intel_bo *bo_2;
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uint32_t *ptr_cpu;
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uint32_t *ptr2_cpu;
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int dma_buf_fd, dma_buf2_fd, i;
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int local_fd;
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drm_intel_bufmgr *local_bufmgr;
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struct intel_batchbuffer *local_batch;
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/* recreate process local variables */
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local_fd = drm_open_driver(DRIVER_INTEL);
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local_bufmgr = drm_intel_bufmgr_gem_init(local_fd, 4096);
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igt_assert(local_bufmgr);
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local_batch = intel_batchbuffer_alloc(local_bufmgr, intel_get_drm_devid(local_fd));
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igt_assert(local_batch);
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bo_1 = drm_intel_bo_alloc(local_bufmgr, "BO 1", width * height * 4, 4096);
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dma_buf_fd = prime_handle_to_fd_for_mmap(local_fd, bo_1->handle);
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igt_skip_on(errno == EINVAL);
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ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
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MAP_SHARED, dma_buf_fd, 0);
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igt_assert(ptr_cpu != MAP_FAILED);
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bo_2 = drm_intel_bo_alloc(local_bufmgr, "BO 2", width * height * 4, 4096);
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dma_buf2_fd = prime_handle_to_fd_for_mmap(local_fd, bo_2->handle);
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ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
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MAP_SHARED, dma_buf2_fd, 0);
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igt_assert(ptr2_cpu != MAP_FAILED);
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/* Fill up BO 1 with '1's and BO 2 with '0's */
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prime_sync_start(dma_buf_fd, true);
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memset(ptr_cpu, 0x11, width * height);
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prime_sync_end(dma_buf_fd, true);
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prime_sync_start(dma_buf2_fd, true);
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memset(ptr2_cpu, 0x00, width * height);
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prime_sync_end(dma_buf2_fd, true);
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/* Copy BO 1 into BO 2, using blitter. */
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intel_copy_bo(local_batch, bo_2, bo_1, width * height);
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usleep(0); /* let someone else claim the mutex */
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/* Compare BOs. If prime_sync_* were executed properly, the caches
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* should be synced. */
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prime_sync_start(dma_buf2_fd, false);
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for (i = 0; i < (width * height) / 4; i++)
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igt_fail_on_f(ptr2_cpu[i] != 0x11111111, "Found 0x%08x at offset 0x%08x\n", ptr2_cpu[i], i);
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prime_sync_end(dma_buf2_fd, false);
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drm_intel_bo_unreference(bo_1);
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drm_intel_bo_unreference(bo_2);
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munmap(ptr_cpu, width * height);
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munmap(ptr2_cpu, width * height);
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close(dma_buf_fd);
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close(dma_buf2_fd);
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intel_batchbuffer_free(local_batch);
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drm_intel_bufmgr_destroy(local_bufmgr);
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close(local_fd);
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}
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/*
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* Constantly interrupt concurrent blits to stress out prime_sync_* and make
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* sure these ioctl errors are handled accordingly.
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*
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* Important to note that in case of failure (e.g. in a case where the ioctl
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* wouldn't try again in a return error) this test does not reliably catch the
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* problem with 100% of accuracy.
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*/
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static void test_ioctl_errors(void)
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{
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int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
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/* Ensure we can do at least one child */
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intel_require_memory(2, width*height*4, CHECK_RAM);
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for (int num_children = 1; num_children <= 8 *ncpus; num_children <<= 1) {
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uint64_t required, total;
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igt_info("Spawing %d interruptible children\n", num_children);
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if (!__intel_check_memory(2*num_children,
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width*height*4,
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CHECK_RAM,
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&required, &total)) {
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igt_debug("Estimated that we need %'lluMiB for test, but only have %'lluMiB\n",
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(long long)(required >> 20),
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(long long)(total >> 20));
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break;
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}
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igt_fork(child, num_children)
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igt_while_interruptible(true) blit_and_cmp();
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igt_waitchildren();
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}
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}
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igt_main
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{
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igt_fixture {
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fd = drm_open_driver(DRIVER_INTEL);
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igt_require_gem(fd);
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bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
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batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
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}
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/* Cache coherency and the eviction are pretty much unpredictable, so
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* reproducing boils down to trial and error to hit different scenarios.
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* TODO: We may want to improve tests a bit by picking random subranges. */
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igt_subtest("read") {
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igt_until_timeout(5) {
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int stale = test_read_flush();
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igt_fail_on_f(stale,
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"num of stale cache lines %d\n", stale);
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}
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}
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igt_subtest("write") {
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igt_until_timeout(5) {
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int stale = test_write_flush();
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igt_fail_on_f(stale,
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"num of stale cache lines %d\n", stale);
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}
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}
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igt_subtest("ioctl-errors") {
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igt_info("exercising concurrent blit to get ioctl errors\n");
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test_ioctl_errors();
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}
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igt_fixture {
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intel_batchbuffer_free(batch);
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drm_intel_bufmgr_destroy(bufmgr);
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close(fd);
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}
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}
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