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217 lines
5.3 KiB
217 lines
5.3 KiB
/*
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* Copyright © 2006 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#ifndef _INTEL_BIOS_H_
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#define _INTEL_BIOS_H_
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#include <stdint.h>
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#define DEVICE_HANDLE_CRT 0x01
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#define DEVICE_HANDLE_EFP1 0x04
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#define DEVICE_HANDLE_EFP2 0x40
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#define DEVICE_HANDLE_EFP3 0x20
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#define DEVICE_HANDLE_EFP4 0x10
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#define DEVICE_HANDLE_LPF1 0x08
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#define DEVICE_HANDLE_LFP2 0x80
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#define DEVICE_TYPE_DP_DVI 0x68d6
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#define DEVICE_TYPE_DVI 0x68d2
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#define DEVICE_TYPE_MIPI 0x7cc2
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struct bdb_legacy_child_devices {
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uint8_t child_dev_size;
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uint8_t devices[0]; /* presumably 7 * 33 */
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} __attribute__ ((packed));
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#define BDB_DRIVER_NO_LVDS 0
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#define BDB_DRIVER_INT_LVDS 1
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#define BDB_DRIVER_SDVO_LVDS 2
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#define BDB_DRIVER_EDP 3
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struct edp_power_seq {
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uint16_t t3;
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uint16_t t7;
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uint16_t t9;
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uint16_t t10;
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uint16_t t12;
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} __attribute__ ((packed));
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/* Block 52 contains MiPi Panel info
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* 6 such enteries will there. Index into correct
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* entery is based on the panel_index in #40 LFP
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*/
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#define MAX_MIPI_CONFIGURATIONS 6
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struct mipi_config {
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uint16_t panel_id;
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/* General Params */
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uint32_t dithering:1;
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uint32_t rsvd1:1;
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uint32_t panel_type:1;
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uint32_t panel_arch_type:2;
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uint32_t cmd_mode:1;
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uint32_t vtm:2;
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uint32_t cabc:1;
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uint32_t pwm_blc:1;
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/* Bit 13:10
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* 000 - Reserved, 001 - RGB565, 002 - RGB666,
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* 011 - RGB666Loosely packed, 100 - RGB888,
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* others - rsvd
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*/
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uint32_t videomode_color_format:4;
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/* Bit 15:14
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* 0 - No rotation, 1 - 90 degree
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* 2 - 180 degree, 3 - 270 degree
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*/
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uint32_t rotation:2;
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uint32_t bta:1;
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uint32_t rsvd2:15;
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/* 2 byte Port Description */
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uint16_t dual_link:2;
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uint16_t lane_cnt:2;
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uint16_t pixel_overlap:3;
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uint16_t rsvd3:9;
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/* 2 byte DSI COntroller params */
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/* 0 - Using DSI PHY, 1 - TE usage */
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uint16_t dsi_usage:1;
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uint16_t rsvd4:15;
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uint8_t rsvd5[5];
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uint32_t dsi_ddr_clk;
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uint32_t bridge_ref_clk;
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uint8_t byte_clk_sel:2;
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uint8_t rsvd6:6;
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/* DPHY Flags */
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uint16_t dphy_param_valid:1;
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uint16_t eot_disabled:1;
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uint16_t clk_stop:1;
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uint16_t rsvd7:13;
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uint32_t hs_tx_timeout;
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uint32_t lp_rx_timeout;
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uint32_t turn_around_timeout;
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uint32_t device_reset_timer;
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uint32_t master_init_timer;
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uint32_t dbi_bw_timer;
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uint32_t lp_byte_clk_val;
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/* 4 byte Dphy Params */
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uint32_t prepare_cnt:6;
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uint32_t rsvd8:2;
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uint32_t clk_zero_cnt:8;
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uint32_t trail_cnt:5;
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uint32_t rsvd9:3;
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uint32_t exit_zero_cnt:6;
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uint32_t rsvd10:2;
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uint32_t clk_lane_switch_cnt;
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uint32_t hl_switch_cnt;
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uint32_t rsvd11[6];
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/* timings based on dphy spec */
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uint8_t tclk_miss;
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uint8_t tclk_post;
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uint8_t rsvd12;
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uint8_t tclk_pre;
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uint8_t tclk_prepare;
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uint8_t tclk_settle;
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uint8_t tclk_term_enable;
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uint8_t tclk_trail;
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uint16_t tclk_prepare_clkzero;
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uint8_t rsvd13;
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uint8_t td_term_enable;
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uint8_t teot;
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uint8_t ths_exit;
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uint8_t ths_prepare;
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uint16_t ths_prepare_hszero;
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uint8_t rsvd14;
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uint8_t ths_settle;
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uint8_t ths_skip;
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uint8_t ths_trail;
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uint8_t tinit;
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uint8_t tlpx;
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uint8_t rsvd15[3];
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/* GPIOs */
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uint8_t panel_enable;
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uint8_t bl_enable;
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uint8_t pwm_enable;
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uint8_t reset_r_n;
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uint8_t pwr_down_r;
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uint8_t stdby_r_n;
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} __attribute__ ((packed));
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/* Block 52 contains MiPi configuration block
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* 6 * bdb_mipi_config, followed by 6 pps data
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* block below
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*/
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struct mipi_pps_data {
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uint16_t panel_on_delay;
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uint16_t bl_enable_delay;
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uint16_t bl_disable_delay;
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uint16_t panel_off_delay;
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uint16_t panel_power_cycle_delay;
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} __attribute__ ((packed));
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/* MIPI Sequence Block definitions */
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enum mipi_seq {
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MIPI_SEQ_END = 0,
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MIPI_SEQ_ASSERT_RESET,
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MIPI_SEQ_INIT_OTP,
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MIPI_SEQ_DISPLAY_ON,
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MIPI_SEQ_DISPLAY_OFF,
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MIPI_SEQ_DEASSERT_RESET,
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MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */
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MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */
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MIPI_SEQ_TEAR_ON, /* sequence block v2+ */
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MIPI_SEQ_TEAR_OFF, /* sequence block v3+ */
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MIPI_SEQ_POWER_ON, /* sequence block v3+ */
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MIPI_SEQ_POWER_OFF, /* sequence block v3+ */
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MIPI_SEQ_MAX
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};
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enum mipi_seq_element {
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MIPI_SEQ_ELEM_END = 0,
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MIPI_SEQ_ELEM_SEND_PKT,
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MIPI_SEQ_ELEM_DELAY,
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MIPI_SEQ_ELEM_GPIO,
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MIPI_SEQ_ELEM_I2C, /* sequence block v2+ */
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MIPI_SEQ_ELEM_SPI, /* sequence block v3+ */
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MIPI_SEQ_ELEM_PMIC, /* sequence block v3+ */
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MIPI_SEQ_ELEM_MAX
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};
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#endif /* _INTEL_BIOS_H_ */
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