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360 lines
10 KiB
360 lines
10 KiB
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <stdlib.h>
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#include <stdint.h>
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#include <stddef.h>
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#include <errno.h>
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#include "private.h"
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#include "nvif/class.h"
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static int
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abi16_chan_nv04(struct nouveau_object *obj)
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{
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struct nouveau_drm *drm = nouveau_drm(obj);
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struct nv04_fifo *nv04 = obj->data;
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struct drm_nouveau_channel_alloc req = {
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.fb_ctxdma_handle = nv04->vram,
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.tt_ctxdma_handle = nv04->gart
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};
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int ret;
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ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
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&req, sizeof(req));
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if (ret)
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return ret;
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nv04->base.channel = req.channel;
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nv04->base.pushbuf = req.pushbuf_domains;
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nv04->notify = req.notifier_handle;
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nv04->base.object->handle = req.channel;
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nv04->base.object->length = sizeof(*nv04);
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return 0;
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}
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static int
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abi16_chan_nvc0(struct nouveau_object *obj)
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{
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struct nouveau_drm *drm = nouveau_drm(obj);
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struct drm_nouveau_channel_alloc req = {};
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struct nvc0_fifo *nvc0 = obj->data;
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int ret;
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ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
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&req, sizeof(req));
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if (ret)
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return ret;
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nvc0->base.channel = req.channel;
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nvc0->base.pushbuf = req.pushbuf_domains;
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nvc0->notify = req.notifier_handle;
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nvc0->base.object->handle = req.channel;
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nvc0->base.object->length = sizeof(*nvc0);
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return 0;
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}
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static int
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abi16_chan_nve0(struct nouveau_object *obj)
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{
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struct nouveau_drm *drm = nouveau_drm(obj);
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struct drm_nouveau_channel_alloc req = {};
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struct nve0_fifo *nve0 = obj->data;
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int ret;
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if (obj->length > offsetof(struct nve0_fifo, engine)) {
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req.fb_ctxdma_handle = 0xffffffff;
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req.tt_ctxdma_handle = nve0->engine;
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}
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ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
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&req, sizeof(req));
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if (ret)
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return ret;
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nve0->base.channel = req.channel;
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nve0->base.pushbuf = req.pushbuf_domains;
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nve0->notify = req.notifier_handle;
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nve0->base.object->handle = req.channel;
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nve0->base.object->length = sizeof(*nve0);
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return 0;
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}
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static int
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abi16_engobj(struct nouveau_object *obj)
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{
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struct nouveau_drm *drm = nouveau_drm(obj);
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struct drm_nouveau_grobj_alloc req = {
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.channel = obj->parent->handle,
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.handle = obj->handle,
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.class = obj->oclass,
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};
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int ret;
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/* Older kernel versions did not have the concept of nouveau-
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* specific classes and abused some NVIDIA-assigned ones for
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* a SW class. The ABI16 layer has compatibility in place to
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* translate these older identifiers to the newer ones.
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*
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* Clients that have been updated to use NVIF are required to
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* use the newer class identifiers, which means that they'll
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* break if running on an older kernel.
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*
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* To handle this case, when using ABI16, we translate to the
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* older values which work on any kernel.
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*/
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switch (req.class) {
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case NVIF_CLASS_SW_NV04 : req.class = 0x006e; break;
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case NVIF_CLASS_SW_NV10 : req.class = 0x016e; break;
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case NVIF_CLASS_SW_NV50 : req.class = 0x506e; break;
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case NVIF_CLASS_SW_GF100: req.class = 0x906e; break;
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default:
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break;
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}
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ret = drmCommandWrite(drm->fd, DRM_NOUVEAU_GROBJ_ALLOC,
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&req, sizeof(req));
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if (ret)
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return ret;
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obj->length = sizeof(struct nouveau_object *);
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return 0;
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}
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static int
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abi16_ntfy(struct nouveau_object *obj)
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{
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struct nouveau_drm *drm = nouveau_drm(obj);
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struct nv04_notify *ntfy = obj->data;
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struct drm_nouveau_notifierobj_alloc req = {
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.channel = obj->parent->handle,
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.handle = ntfy->object->handle,
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.size = ntfy->length,
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};
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int ret;
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ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_NOTIFIEROBJ_ALLOC,
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&req, sizeof(req));
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if (ret)
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return ret;
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ntfy->offset = req.offset;
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ntfy->object->length = sizeof(*ntfy);
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return 0;
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}
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drm_private int
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abi16_sclass(struct nouveau_object *obj, struct nouveau_sclass **psclass)
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{
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struct nouveau_sclass *sclass;
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struct nouveau_device *dev;
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if (!(sclass = calloc(8, sizeof(*sclass))))
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return -ENOMEM;
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*psclass = sclass;
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switch (obj->oclass) {
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case NOUVEAU_FIFO_CHANNEL_CLASS:
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/* Older kernel versions were exposing the wrong video engine
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* classes on certain G98:GF100 boards. This has since been
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* corrected, but ABI16 has compatibility in place to avoid
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* breaking older userspace.
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*
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* Clients that have been updated to use NVIF are required to
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* use the correct classes, which means that they'll break if
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* running on an older kernel.
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*
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* To handle this issue, if using the older kernel interfaces,
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* we'll magic up a list containing the vdec classes that the
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* kernel will accept for these boards. Clients should make
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* use of this information instead of hardcoding classes for
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* specific chipsets.
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*/
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dev = (struct nouveau_device *)obj->parent;
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if (dev->chipset >= 0x98 &&
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dev->chipset != 0xa0 &&
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dev->chipset < 0xc0) {
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*sclass++ = (struct nouveau_sclass){
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GT212_MSVLD, -1, -1
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};
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*sclass++ = (struct nouveau_sclass){
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GT212_MSPDEC, -1, -1
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};
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*sclass++ = (struct nouveau_sclass){
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GT212_MSPPP, -1, -1
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};
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}
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break;
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default:
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break;
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}
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return sclass - *psclass;
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}
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drm_private void
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abi16_delete(struct nouveau_object *obj)
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{
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struct nouveau_drm *drm = nouveau_drm(obj);
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if (obj->oclass == NOUVEAU_FIFO_CHANNEL_CLASS) {
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struct drm_nouveau_channel_free req;
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req.channel = obj->handle;
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drmCommandWrite(drm->fd, DRM_NOUVEAU_CHANNEL_FREE,
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&req, sizeof(req));
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} else {
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struct drm_nouveau_gpuobj_free req;
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req.channel = obj->parent->handle;
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req.handle = obj->handle;
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drmCommandWrite(drm->fd, DRM_NOUVEAU_GPUOBJ_FREE,
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&req, sizeof(req));
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}
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}
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drm_private bool
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abi16_object(struct nouveau_object *obj, int (**func)(struct nouveau_object *))
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{
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struct nouveau_object *parent = obj->parent;
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/* nouveau_object::length is (ab)used to determine whether the
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* object is a legacy object (!=0), or a real NVIF object.
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*/
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if ((parent->length != 0 && parent->oclass == NOUVEAU_DEVICE_CLASS) ||
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(parent->length == 0 && parent->oclass == NV_DEVICE)) {
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if (obj->oclass == NOUVEAU_FIFO_CHANNEL_CLASS) {
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struct nouveau_device *dev = (void *)parent;
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if (dev->chipset < 0xc0)
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*func = abi16_chan_nv04;
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else
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if (dev->chipset < 0xe0)
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*func = abi16_chan_nvc0;
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else
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*func = abi16_chan_nve0;
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return true;
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}
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} else
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if ((parent->length != 0 &&
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parent->oclass == NOUVEAU_FIFO_CHANNEL_CLASS)) {
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if (obj->oclass == NOUVEAU_NOTIFIER_CLASS) {
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*func = abi16_ntfy;
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return true;
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}
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*func = abi16_engobj;
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return false; /* try NVIF, if supported, before calling func */
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}
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*func = NULL;
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return false;
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}
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drm_private void
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abi16_bo_info(struct nouveau_bo *bo, struct drm_nouveau_gem_info *info)
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{
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struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
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nvbo->map_handle = info->map_handle;
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bo->handle = info->handle;
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bo->size = info->size;
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bo->offset = info->offset;
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bo->flags = 0;
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if (info->domain & NOUVEAU_GEM_DOMAIN_VRAM)
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bo->flags |= NOUVEAU_BO_VRAM;
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if (info->domain & NOUVEAU_GEM_DOMAIN_GART)
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bo->flags |= NOUVEAU_BO_GART;
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if (!(info->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG))
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bo->flags |= NOUVEAU_BO_CONTIG;
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if (nvbo->map_handle)
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bo->flags |= NOUVEAU_BO_MAP;
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if (bo->device->chipset >= 0xc0) {
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bo->config.nvc0.memtype = (info->tile_flags & 0xff00) >> 8;
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bo->config.nvc0.tile_mode = info->tile_mode;
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} else
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if (bo->device->chipset >= 0x80 || bo->device->chipset == 0x50) {
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bo->config.nv50.memtype = (info->tile_flags & 0x07f00) >> 8 |
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(info->tile_flags & 0x30000) >> 9;
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bo->config.nv50.tile_mode = info->tile_mode << 4;
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} else {
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bo->config.nv04.surf_flags = info->tile_flags & 7;
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bo->config.nv04.surf_pitch = info->tile_mode;
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}
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}
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drm_private int
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abi16_bo_init(struct nouveau_bo *bo, uint32_t alignment,
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union nouveau_bo_config *config)
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{
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struct nouveau_device *dev = bo->device;
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struct nouveau_drm *drm = nouveau_drm(&dev->object);
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struct drm_nouveau_gem_new req = {};
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struct drm_nouveau_gem_info *info = &req.info;
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int ret;
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if (bo->flags & NOUVEAU_BO_VRAM)
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info->domain |= NOUVEAU_GEM_DOMAIN_VRAM;
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if (bo->flags & NOUVEAU_BO_GART)
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info->domain |= NOUVEAU_GEM_DOMAIN_GART;
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if (!info->domain)
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info->domain |= NOUVEAU_GEM_DOMAIN_VRAM |
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NOUVEAU_GEM_DOMAIN_GART;
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if (bo->flags & NOUVEAU_BO_MAP)
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info->domain |= NOUVEAU_GEM_DOMAIN_MAPPABLE;
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if (bo->flags & NOUVEAU_BO_COHERENT)
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info->domain |= NOUVEAU_GEM_DOMAIN_COHERENT;
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if (!(bo->flags & NOUVEAU_BO_CONTIG))
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info->tile_flags = NOUVEAU_GEM_TILE_NONCONTIG;
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info->size = bo->size;
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req.align = alignment;
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if (config) {
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if (dev->chipset >= 0xc0) {
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info->tile_flags = (config->nvc0.memtype & 0xff) << 8;
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info->tile_mode = config->nvc0.tile_mode;
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} else
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if (dev->chipset >= 0x80 || dev->chipset == 0x50) {
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info->tile_flags = (config->nv50.memtype & 0x07f) << 8 |
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(config->nv50.memtype & 0x180) << 9;
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info->tile_mode = config->nv50.tile_mode >> 4;
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} else {
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info->tile_flags = config->nv04.surf_flags & 7;
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info->tile_mode = config->nv04.surf_pitch;
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}
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}
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if (!nouveau_device(dev)->have_bo_usage)
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info->tile_flags &= 0x0000ff00;
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ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_GEM_NEW,
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&req, sizeof(req));
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if (ret == 0)
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abi16_bo_info(bo, &req.info);
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return ret;
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}
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