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238 lines
7.6 KiB
238 lines
7.6 KiB
@/*****************************************************************************
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@*
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@* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
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@*
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@* Licensed under the Apache License, Version 2.0 (the "License");
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@* you may not use this file except in compliance with the License.
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@* You may obtain a copy of the License at:
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@*
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@* http://www.apache.org/licenses/LICENSE-2.0
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@*
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@* Unless required by applicable law or agreed to in writing, software
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@* distributed under the License is distributed on an "AS IS" BASIS,
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@* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@* See the License for the specific language governing permissions and
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@* limitations under the License.
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@*
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@*****************************************************************************/
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@/**
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@ *******************************************************************************
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@ * @file
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@ * ihevc_itrans_recon_4x4_neon.s
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@ *
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@ * @brief
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@ * contains function definitions for single stage inverse transform
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@ *
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@ * @author
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@ * naveen sr
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@ *
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@ * @par list of functions:
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@ * - ihevc_itrans_recon_4x4()
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@ *
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@ * @remarks
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@ * none
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@ *
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@ *******************************************************************************
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@*/
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@ /**
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@ *******************************************************************************
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@ *
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@ * @brief
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@ * this function performs inverse transform and reconstruction for 4x4
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@ * input block
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@ *
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@ * @par description:
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@ * performs inverse transform and adds the prediction data and clips output
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@ * to 8 bit
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@ *
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@ * @param[in] pi2_src
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@ * input 4x4 coefficients
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@ *
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@ * @param[in] pi2_tmp
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@ * temporary 4x4 buffer for storing inverse
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@ *
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@ * transform
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@ * 1st stage output
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@ *
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@ * @param[in] pu1_pred
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@ * prediction 4x4 block
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@ *
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@ * @param[out] pu1_dst
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@ * output 4x4 block
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@ *
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@ * @param[in] src_strd
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@ * input stride
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@ *
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@ * @param[in] pred_strd
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@ * prediction stride
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@ *
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@ * @param[in] dst_strd
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@ * output stride
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@ *
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@ * @param[in] shift
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@ * output shift
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@ *
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@ * @param[in] zero_cols
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@ * zero columns in pi2_src
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@ *
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@ * @returns void
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@ *
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@ * @remarks
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@ * none
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@ *
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@ *******************************************************************************
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@ */
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@void ihevc_itrans_recon_4x4(word16 *pi2_src,
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@ word16 *pi2_tmp,
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@ uword8 *pu1_pred,
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@ uword8 *pu1_dst,
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@ word32 src_strd,
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@ word32 pred_strd,
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@ word32 dst_strd,
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@ word32 zero_cols)
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@**************variables vs registers*************************
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@ r0 => *pi2_src
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@ r1 => *pi2_tmp
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@ r2 => *pu1_pred
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@ r3 => *pu1_dst
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@ r4 => src_strd
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@ r5 => pred_strd
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@ r6 => dst_strd
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@ r7 => zero_cols
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.equ src_strd_offset, 104
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.equ pred_strd_offset, 108
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.equ dst_strd_offset, 112
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.equ zero_cols_offset, 116
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.text
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.align 4
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.set shift_stage1_idct , 7
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.set shift_stage2_idct , 12
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.globl ihevc_itrans_recon_4x4_a9q
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.extern g_ai2_ihevc_trans_4_transpose
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g_ai2_ihevc_trans_4_transpose_addr:
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.long g_ai2_ihevc_trans_4_transpose - ulbl1 - 8
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.type ihevc_itrans_recon_4x4_a9q, %function
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ihevc_itrans_recon_4x4_a9q:
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stmfd sp!, {r4-r12, r14} @stack stores the values of the arguments
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vpush {d8 - d15}
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ldr r8,g_ai2_ihevc_trans_4_transpose_addr
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ulbl1:
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add r8,r8,pc
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ldr r4,[sp,#src_strd_offset] @loading src_strd
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ldr r5,[sp,#pred_strd_offset] @loading pred_strd
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add r4,r4,r4 @ src_strd in terms of word16
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ldr r6,[sp,#dst_strd_offset] @loading dst_strd
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ldr r7,[sp,#zero_cols_offset] @loading zero_cols
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add r9,r0,r4 @ pi2_src[0] + src_strd
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vld1.16 d4,[r8] @loading first row of g_ai2_ihevc_trans_4_transpose
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@ d4 = {36,64,83,64}
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@index = 3 2 1 0
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add r10,r9,r4, lsl #1 @ 3*src_strd
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add r4,r4,r4
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vld1.16 d1,[r9] @loading pi2_src 2nd row
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vld1.16 d3,[r10] @loading pi2_src 4th row
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vld1.16 d0,[r0],r4 @loading pi2_src 1st row
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vld1.16 d2,[r0],r4 @loading pi2_src 3rd row
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@ first stage computation starts
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vmull.s16 q3,d1,d4[1] @83 * pi2_src[1]
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vmlal.s16 q3,d3,d4[3] @o[0] = 83 * pi2_src[1] + 36 * pi2_src[3]
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vmull.s16 q4,d1,d4[3] @36 * pi2_src[1]
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vld1.32 d22[0], [r2],r5
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vmlsl.s16 q4,d3,d4[1] @o[1] = 36 * pi2_src[1] - 83 * pi2_src[3]
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vaddl.s16 q5,d0,d2 @pi2_src[0] + pi2_src[2]
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vsubl.s16 q6,d0,d2 @pi2_src[0] - pi2_src[2]
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vshl.s32 q5,q5,#6 @e[0] = 64*(pi2_src[0] + pi2_src[2])
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vshl.s32 q6,q6,#6 @e[1] = 64*(pi2_src[0] - pi2_src[2])
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vadd.s32 q7,q5,q3 @((e[0] + o[0] )
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vadd.s32 q8,q6,q4 @((e[1] + o[1])
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vsub.s32 q9,q6,q4 @((e[1] - o[1])
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vsub.s32 q10,q5,q3 @((e[0] - o[0])
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vqrshrn.s32 d0,q7,#shift_stage1_idct @pi2_out[0] = clip_s16((e[0] + o[0] + add)>>shift) )
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vqrshrn.s32 d1,q8,#shift_stage1_idct @pi2_out[1] = clip_s16((e[1] + o[1] + add)>>shift) )
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vqrshrn.s32 d2,q9,#shift_stage1_idct @pi2_out[2] = clip_s16((e[0] - o[0] + add)>>shift) )
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vqrshrn.s32 d3,q10,#shift_stage1_idct @pi2_out[3] = clip_s16((e[0] - o[0] + add)>>shift) )
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vtrn.16 d0,d1
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vtrn.16 d2,d3
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vtrn.32 d0,d2
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vtrn.32 d1,d3
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@ first stage ends
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@ output in d0,d1,d2,d3
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@ second stage starts
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vmull.s16 q3,d1,d4[1] @83 * pi2_src[1]
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vld1.32 d22[1], [r2],r5
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vmlal.s16 q3,d3,d4[3] @o[0] = 83 * pi2_src[1] + 36 * pi2_src[3]
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vmull.s16 q4,d1,d4[3] @36 * pi2_src[1]
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vmlsl.s16 q4,d3,d4[1] @o[1] = 36 * pi2_src[1] - 83 * pi2_src[3]
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vld1.32 d23[0], [r2],r5
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vaddl.s16 q5,d0,d2 @pi2_src[0] + pi2_src[2]
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vsubl.s16 q6,d0,d2 @pi2_src[0] - pi2_src[2]
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vshl.s32 q5,q5,#6 @e[0] = 64*(pi2_src[0] + pi2_src[2])
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vshl.s32 q6,q6,#6 @e[1] = 64*(pi2_src[0] - pi2_src[2])
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vadd.s32 q7,q5,q3 @((e[0] + o[0] )
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vadd.s32 q8,q6,q4 @((e[1] + o[1])
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vsub.s32 q9,q6,q4 @((e[1] - o[1])
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vsub.s32 q10,q5,q3 @((e[0] - o[0])
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vqrshrn.s32 d0,q7,#shift_stage2_idct @pi2_out[0] = clip_s16((e[0] + o[0] + add)>>shift) )
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vqrshrn.s32 d1,q8,#shift_stage2_idct @pi2_out[1] = clip_s16((e[1] + o[1] + add)>>shift) )
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vqrshrn.s32 d2,q9,#shift_stage2_idct @pi2_out[2] = clip_s16((e[0] - o[0] + add)>>shift) )
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vqrshrn.s32 d3,q10,#shift_stage2_idct @pi2_out[3] = clip_s16((e[0] - o[0] + add)>>shift) )
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vld1.32 d23[1], [r2],r5
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vtrn.16 d0,d1
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vtrn.16 d2,d3
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vtrn.32 d0,d2
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vtrn.32 d1,d3
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@ second stage ends
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@ output in d0,d1,d2,d3
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@ second stage computation ends
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@ loading pred
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vaddw.u8 q0,q0,d22 @ pi2_out(16bit) + pu1_pred(8bit)
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vaddw.u8 q1,q1,d23 @ pi2_out(16bit) + pu1_pred(8bit)
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vqmovun.s16 d0,q0 @ clip_u8(pi2_out(16bit) + pu1_pred(8bit))
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vqmovun.s16 d1,q1 @ clip_u8(pi2_out(16bit) + pu1_pred(8bit))
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@ storing destination
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vst1.32 {d0[0]},[r3],r6
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vst1.32 {d0[1]},[r3],r6
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vst1.32 {d1[0]},[r3],r6
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vst1.32 {d1[1]},[r3],r6
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vpop {d8 - d15}
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ldmfd sp!,{r4-r12,r15} @reload the registers from sp
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