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609 lines
22 KiB
609 lines
22 KiB
//===- lib/CodeGen/GlobalISel/GISelKnownBits.cpp --------------*- C++ *-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// Provides analysis for querying information about KnownBits during GISel
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/// passes.
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//
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//===------------------
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#define DEBUG_TYPE "gisel-known-bits"
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using namespace llvm;
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char llvm::GISelKnownBitsAnalysis::ID = 0;
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INITIALIZE_PASS(GISelKnownBitsAnalysis, DEBUG_TYPE,
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"Analysis for ComputingKnownBits", false, true)
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GISelKnownBits::GISelKnownBits(MachineFunction &MF, unsigned MaxDepth)
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: MF(MF), MRI(MF.getRegInfo()), TL(*MF.getSubtarget().getTargetLowering()),
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DL(MF.getFunction().getParent()->getDataLayout()), MaxDepth(MaxDepth) {}
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Align GISelKnownBits::computeKnownAlignment(Register R, unsigned Depth) {
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const MachineInstr *MI = MRI.getVRegDef(R);
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switch (MI->getOpcode()) {
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case TargetOpcode::COPY:
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return computeKnownAlignment(MI->getOperand(1).getReg(), Depth);
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case TargetOpcode::G_FRAME_INDEX: {
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int FrameIdx = MI->getOperand(1).getIndex();
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return MF.getFrameInfo().getObjectAlign(FrameIdx);
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}
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case TargetOpcode::G_INTRINSIC:
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case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
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default:
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return TL.computeKnownAlignForTargetInstr(*this, R, MRI, Depth + 1);
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}
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}
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KnownBits GISelKnownBits::getKnownBits(MachineInstr &MI) {
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assert(MI.getNumExplicitDefs() == 1 &&
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"expected single return generic instruction");
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return getKnownBits(MI.getOperand(0).getReg());
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}
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KnownBits GISelKnownBits::getKnownBits(Register R) {
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const LLT Ty = MRI.getType(R);
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APInt DemandedElts =
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Ty.isVector() ? APInt::getAllOnesValue(Ty.getNumElements()) : APInt(1, 1);
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return getKnownBits(R, DemandedElts);
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}
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KnownBits GISelKnownBits::getKnownBits(Register R, const APInt &DemandedElts,
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unsigned Depth) {
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// For now, we only maintain the cache during one request.
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assert(ComputeKnownBitsCache.empty() && "Cache should have been cleared");
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KnownBits Known;
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computeKnownBitsImpl(R, Known, DemandedElts);
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ComputeKnownBitsCache.clear();
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return Known;
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}
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bool GISelKnownBits::signBitIsZero(Register R) {
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LLT Ty = MRI.getType(R);
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unsigned BitWidth = Ty.getScalarSizeInBits();
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return maskedValueIsZero(R, APInt::getSignMask(BitWidth));
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}
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APInt GISelKnownBits::getKnownZeroes(Register R) {
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return getKnownBits(R).Zero;
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}
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APInt GISelKnownBits::getKnownOnes(Register R) { return getKnownBits(R).One; }
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LLVM_ATTRIBUTE_UNUSED static void
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dumpResult(const MachineInstr &MI, const KnownBits &Known, unsigned Depth) {
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dbgs() << "[" << Depth << "] Compute known bits: " << MI << "[" << Depth
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<< "] Computed for: " << MI << "[" << Depth << "] Known: 0x"
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<< (Known.Zero | Known.One).toString(16, false) << "\n"
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<< "[" << Depth << "] Zero: 0x" << Known.Zero.toString(16, false)
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<< "\n"
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<< "[" << Depth << "] One: 0x" << Known.One.toString(16, false)
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<< "\n";
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}
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/// Compute known bits for the intersection of \p Src0 and \p Src1
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void GISelKnownBits::computeKnownBitsMin(Register Src0, Register Src1,
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KnownBits &Known,
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const APInt &DemandedElts,
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unsigned Depth) {
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// Test src1 first, since we canonicalize simpler expressions to the RHS.
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computeKnownBitsImpl(Src1, Known, DemandedElts, Depth);
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// If we don't know any bits, early out.
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if (Known.isUnknown())
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return;
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KnownBits Known2;
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computeKnownBitsImpl(Src0, Known2, DemandedElts, Depth);
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// Only known if known in both the LHS and RHS.
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Known = KnownBits::commonBits(Known, Known2);
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}
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void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
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const APInt &DemandedElts,
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unsigned Depth) {
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MachineInstr &MI = *MRI.getVRegDef(R);
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unsigned Opcode = MI.getOpcode();
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LLT DstTy = MRI.getType(R);
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// Handle the case where this is called on a register that does not have a
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// type constraint (i.e. it has a register class constraint instead). This is
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// unlikely to occur except by looking through copies but it is possible for
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// the initial register being queried to be in this state.
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if (!DstTy.isValid()) {
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Known = KnownBits();
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return;
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}
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unsigned BitWidth = DstTy.getSizeInBits();
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auto CacheEntry = ComputeKnownBitsCache.find(R);
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if (CacheEntry != ComputeKnownBitsCache.end()) {
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Known = CacheEntry->second;
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LLVM_DEBUG(dbgs() << "Cache hit at ");
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LLVM_DEBUG(dumpResult(MI, Known, Depth));
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assert(Known.getBitWidth() == BitWidth && "Cache entry size doesn't match");
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return;
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}
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Known = KnownBits(BitWidth); // Don't know anything
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if (DstTy.isVector())
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return; // TODO: Handle vectors.
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// Depth may get bigger than max depth if it gets passed to a different
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// GISelKnownBits object.
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// This may happen when say a generic part uses a GISelKnownBits object
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// with some max depth, but then we hit TL.computeKnownBitsForTargetInstr
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// which creates a new GISelKnownBits object with a different and smaller
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// depth. If we just check for equality, we would never exit if the depth
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// that is passed down to the target specific GISelKnownBits object is
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// already bigger than its max depth.
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if (Depth >= getMaxDepth())
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return;
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if (!DemandedElts)
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return; // No demanded elts, better to assume we don't know anything.
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KnownBits Known2;
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switch (Opcode) {
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default:
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TL.computeKnownBitsForTargetInstr(*this, R, Known, DemandedElts, MRI,
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Depth);
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break;
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case TargetOpcode::COPY:
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case TargetOpcode::G_PHI:
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case TargetOpcode::PHI: {
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Known.One = APInt::getAllOnesValue(BitWidth);
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Known.Zero = APInt::getAllOnesValue(BitWidth);
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// Destination registers should not have subregisters at this
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// point of the pipeline, otherwise the main live-range will be
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// defined more than once, which is against SSA.
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assert(MI.getOperand(0).getSubReg() == 0 && "Is this code in SSA?");
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// Record in the cache that we know nothing for MI.
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// This will get updated later and in the meantime, if we reach that
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// phi again, because of a loop, we will cut the search thanks to this
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// cache entry.
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// We could actually build up more information on the phi by not cutting
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// the search, but that additional information is more a side effect
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// than an intended choice.
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// Therefore, for now, save on compile time until we derive a proper way
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// to derive known bits for PHIs within loops.
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ComputeKnownBitsCache[R] = KnownBits(BitWidth);
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// PHI's operand are a mix of registers and basic blocks interleaved.
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// We only care about the register ones.
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for (unsigned Idx = 1; Idx < MI.getNumOperands(); Idx += 2) {
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const MachineOperand &Src = MI.getOperand(Idx);
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Register SrcReg = Src.getReg();
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// Look through trivial copies and phis but don't look through trivial
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// copies or phis of the form `%1:(s32) = OP %0:gpr32`, known-bits
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// analysis is currently unable to determine the bit width of a
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// register class.
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//
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// We can't use NoSubRegister by name as it's defined by each target but
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// it's always defined to be 0 by tablegen.
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if (SrcReg.isVirtual() && Src.getSubReg() == 0 /*NoSubRegister*/ &&
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MRI.getType(SrcReg).isValid()) {
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// For COPYs we don't do anything, don't increase the depth.
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computeKnownBitsImpl(SrcReg, Known2, DemandedElts,
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Depth + (Opcode != TargetOpcode::COPY));
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Known = KnownBits::commonBits(Known, Known2);
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// If we reach a point where we don't know anything
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// just stop looking through the operands.
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if (Known.One == 0 && Known.Zero == 0)
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break;
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} else {
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// We know nothing.
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Known = KnownBits(BitWidth);
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break;
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}
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}
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break;
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}
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case TargetOpcode::G_CONSTANT: {
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auto CstVal = getConstantVRegVal(R, MRI);
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if (!CstVal)
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break;
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Known.One = *CstVal;
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Known.Zero = ~Known.One;
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break;
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}
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case TargetOpcode::G_FRAME_INDEX: {
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int FrameIdx = MI.getOperand(1).getIndex();
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TL.computeKnownBitsForFrameIndex(FrameIdx, Known, MF);
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break;
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}
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case TargetOpcode::G_SUB: {
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
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Depth + 1);
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Known = KnownBits::computeForAddSub(/*Add*/ false, /*NSW*/ false, Known,
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Known2);
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break;
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}
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case TargetOpcode::G_XOR: {
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computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
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Depth + 1);
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Known ^= Known2;
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break;
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}
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case TargetOpcode::G_PTR_ADD: {
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// G_PTR_ADD is like G_ADD. FIXME: Is this true for all targets?
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LLT Ty = MRI.getType(MI.getOperand(1).getReg());
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if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace()))
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break;
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LLVM_FALLTHROUGH;
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}
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case TargetOpcode::G_ADD: {
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
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Depth + 1);
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Known =
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KnownBits::computeForAddSub(/*Add*/ true, /*NSW*/ false, Known, Known2);
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break;
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}
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case TargetOpcode::G_AND: {
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// If either the LHS or the RHS are Zero, the result is zero.
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computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
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Depth + 1);
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Known &= Known2;
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break;
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}
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case TargetOpcode::G_OR: {
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// If either the LHS or the RHS are Zero, the result is zero.
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computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
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Depth + 1);
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Known |= Known2;
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break;
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}
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case TargetOpcode::G_MUL: {
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computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
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Depth + 1);
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Known = KnownBits::computeForMul(Known, Known2);
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break;
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}
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case TargetOpcode::G_SELECT: {
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computeKnownBitsMin(MI.getOperand(2).getReg(), MI.getOperand(3).getReg(),
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Known, DemandedElts, Depth + 1);
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break;
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}
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case TargetOpcode::G_SMIN: {
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// TODO: Handle clamp pattern with number of sign bits
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KnownBits KnownRHS;
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(2).getReg(), KnownRHS, DemandedElts,
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Depth + 1);
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Known = KnownBits::smin(Known, KnownRHS);
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break;
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}
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case TargetOpcode::G_SMAX: {
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// TODO: Handle clamp pattern with number of sign bits
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KnownBits KnownRHS;
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(2).getReg(), KnownRHS, DemandedElts,
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Depth + 1);
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Known = KnownBits::smax(Known, KnownRHS);
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break;
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}
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case TargetOpcode::G_UMIN: {
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KnownBits KnownRHS;
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known,
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DemandedElts, Depth + 1);
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computeKnownBitsImpl(MI.getOperand(2).getReg(), KnownRHS,
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DemandedElts, Depth + 1);
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Known = KnownBits::umin(Known, KnownRHS);
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break;
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}
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case TargetOpcode::G_UMAX: {
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KnownBits KnownRHS;
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known,
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DemandedElts, Depth + 1);
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computeKnownBitsImpl(MI.getOperand(2).getReg(), KnownRHS,
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DemandedElts, Depth + 1);
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Known = KnownBits::umax(Known, KnownRHS);
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break;
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}
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case TargetOpcode::G_FCMP:
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case TargetOpcode::G_ICMP: {
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if (TL.getBooleanContents(DstTy.isVector(),
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Opcode == TargetOpcode::G_FCMP) ==
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TargetLowering::ZeroOrOneBooleanContent &&
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BitWidth > 1)
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Known.Zero.setBitsFrom(1);
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break;
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}
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case TargetOpcode::G_SEXT: {
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
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Depth + 1);
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// If the sign bit is known to be zero or one, then sext will extend
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// it to the top bits, else it will just zext.
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Known = Known.sext(BitWidth);
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break;
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}
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case TargetOpcode::G_ANYEXT: {
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
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Depth + 1);
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Known = Known.anyext(BitWidth);
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break;
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}
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case TargetOpcode::G_LOAD: {
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const MachineMemOperand *MMO = *MI.memoperands_begin();
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if (const MDNode *Ranges = MMO->getRanges()) {
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computeKnownBitsFromRangeMetadata(*Ranges, Known);
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}
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break;
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}
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case TargetOpcode::G_ZEXTLOAD: {
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// Everything above the retrieved bits is zero
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Known.Zero.setBitsFrom((*MI.memoperands_begin())->getSizeInBits());
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break;
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}
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case TargetOpcode::G_ASHR: {
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KnownBits LHSKnown, RHSKnown;
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computeKnownBitsImpl(MI.getOperand(1).getReg(), LHSKnown, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,
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Depth + 1);
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Known = KnownBits::ashr(LHSKnown, RHSKnown);
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break;
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}
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case TargetOpcode::G_LSHR: {
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KnownBits LHSKnown, RHSKnown;
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computeKnownBitsImpl(MI.getOperand(1).getReg(), LHSKnown, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,
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Depth + 1);
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Known = KnownBits::lshr(LHSKnown, RHSKnown);
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break;
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}
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case TargetOpcode::G_SHL: {
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KnownBits LHSKnown, RHSKnown;
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computeKnownBitsImpl(MI.getOperand(1).getReg(), LHSKnown, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,
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Depth + 1);
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Known = KnownBits::shl(LHSKnown, RHSKnown);
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break;
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}
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case TargetOpcode::G_INTTOPTR:
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case TargetOpcode::G_PTRTOINT:
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// Fall through and handle them the same as zext/trunc.
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LLVM_FALLTHROUGH;
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case TargetOpcode::G_ZEXT:
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case TargetOpcode::G_TRUNC: {
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Register SrcReg = MI.getOperand(1).getReg();
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LLT SrcTy = MRI.getType(SrcReg);
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unsigned SrcBitWidth = SrcTy.isPointer()
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? DL.getIndexSizeInBits(SrcTy.getAddressSpace())
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: SrcTy.getSizeInBits();
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assert(SrcBitWidth && "SrcBitWidth can't be zero");
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Known = Known.zextOrTrunc(SrcBitWidth);
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computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);
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Known = Known.zextOrTrunc(BitWidth);
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if (BitWidth > SrcBitWidth)
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Known.Zero.setBitsFrom(SrcBitWidth);
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break;
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}
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case TargetOpcode::G_MERGE_VALUES: {
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unsigned NumOps = MI.getNumOperands();
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unsigned OpSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
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for (unsigned I = 0; I != NumOps - 1; ++I) {
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KnownBits SrcOpKnown;
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computeKnownBitsImpl(MI.getOperand(I + 1).getReg(), SrcOpKnown,
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DemandedElts, Depth + 1);
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Known.insertBits(SrcOpKnown, I * OpSize);
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}
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break;
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}
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case TargetOpcode::G_UNMERGE_VALUES: {
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unsigned NumOps = MI.getNumOperands();
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Register SrcReg = MI.getOperand(NumOps - 1).getReg();
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if (MRI.getType(SrcReg).isVector())
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return; // TODO: Handle vectors.
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KnownBits SrcOpKnown;
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computeKnownBitsImpl(SrcReg, SrcOpKnown, DemandedElts, Depth + 1);
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// Figure out the result operand index
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unsigned DstIdx = 0;
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for (; DstIdx != NumOps - 1 && MI.getOperand(DstIdx).getReg() != R;
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++DstIdx)
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;
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Known = SrcOpKnown.extractBits(BitWidth, BitWidth * DstIdx);
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break;
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}
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case TargetOpcode::G_BSWAP: {
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Register SrcReg = MI.getOperand(1).getReg();
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computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);
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Known.byteSwap();
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break;
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}
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case TargetOpcode::G_BITREVERSE: {
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Register SrcReg = MI.getOperand(1).getReg();
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computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);
|
|
Known.reverseBits();
|
|
break;
|
|
}
|
|
}
|
|
|
|
assert(!Known.hasConflict() && "Bits known to be one AND zero?");
|
|
LLVM_DEBUG(dumpResult(MI, Known, Depth));
|
|
|
|
// Update the cache.
|
|
ComputeKnownBitsCache[R] = Known;
|
|
}
|
|
|
|
/// Compute number of sign bits for the intersection of \p Src0 and \p Src1
|
|
unsigned GISelKnownBits::computeNumSignBitsMin(Register Src0, Register Src1,
|
|
const APInt &DemandedElts,
|
|
unsigned Depth) {
|
|
// Test src1 first, since we canonicalize simpler expressions to the RHS.
|
|
unsigned Src1SignBits = computeNumSignBits(Src1, DemandedElts, Depth);
|
|
if (Src1SignBits == 1)
|
|
return 1;
|
|
return std::min(computeNumSignBits(Src0, DemandedElts, Depth), Src1SignBits);
|
|
}
|
|
|
|
unsigned GISelKnownBits::computeNumSignBits(Register R,
|
|
const APInt &DemandedElts,
|
|
unsigned Depth) {
|
|
MachineInstr &MI = *MRI.getVRegDef(R);
|
|
unsigned Opcode = MI.getOpcode();
|
|
|
|
if (Opcode == TargetOpcode::G_CONSTANT)
|
|
return MI.getOperand(1).getCImm()->getValue().getNumSignBits();
|
|
|
|
if (Depth == getMaxDepth())
|
|
return 1;
|
|
|
|
if (!DemandedElts)
|
|
return 1; // No demanded elts, better to assume we don't know anything.
|
|
|
|
LLT DstTy = MRI.getType(R);
|
|
const unsigned TyBits = DstTy.getScalarSizeInBits();
|
|
|
|
// Handle the case where this is called on a register that does not have a
|
|
// type constraint. This is unlikely to occur except by looking through copies
|
|
// but it is possible for the initial register being queried to be in this
|
|
// state.
|
|
if (!DstTy.isValid())
|
|
return 1;
|
|
|
|
unsigned FirstAnswer = 1;
|
|
switch (Opcode) {
|
|
case TargetOpcode::COPY: {
|
|
MachineOperand &Src = MI.getOperand(1);
|
|
if (Src.getReg().isVirtual() && Src.getSubReg() == 0 &&
|
|
MRI.getType(Src.getReg()).isValid()) {
|
|
// Don't increment Depth for this one since we didn't do any work.
|
|
return computeNumSignBits(Src.getReg(), DemandedElts, Depth);
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
case TargetOpcode::G_SEXT: {
|
|
Register Src = MI.getOperand(1).getReg();
|
|
LLT SrcTy = MRI.getType(Src);
|
|
unsigned Tmp = DstTy.getScalarSizeInBits() - SrcTy.getScalarSizeInBits();
|
|
return computeNumSignBits(Src, DemandedElts, Depth + 1) + Tmp;
|
|
}
|
|
case TargetOpcode::G_SEXT_INREG: {
|
|
// Max of the input and what this extends.
|
|
Register Src = MI.getOperand(1).getReg();
|
|
unsigned SrcBits = MI.getOperand(2).getImm();
|
|
unsigned InRegBits = TyBits - SrcBits + 1;
|
|
return std::max(computeNumSignBits(Src, DemandedElts, Depth + 1), InRegBits);
|
|
}
|
|
case TargetOpcode::G_SEXTLOAD: {
|
|
// FIXME: We need an in-memory type representation.
|
|
if (DstTy.isVector())
|
|
return 1;
|
|
|
|
// e.g. i16->i32 = '17' bits known.
|
|
const MachineMemOperand *MMO = *MI.memoperands_begin();
|
|
return TyBits - MMO->getSizeInBits() + 1;
|
|
}
|
|
case TargetOpcode::G_ZEXTLOAD: {
|
|
// FIXME: We need an in-memory type representation.
|
|
if (DstTy.isVector())
|
|
return 1;
|
|
|
|
// e.g. i16->i32 = '16' bits known.
|
|
const MachineMemOperand *MMO = *MI.memoperands_begin();
|
|
return TyBits - MMO->getSizeInBits();
|
|
}
|
|
case TargetOpcode::G_TRUNC: {
|
|
Register Src = MI.getOperand(1).getReg();
|
|
LLT SrcTy = MRI.getType(Src);
|
|
|
|
// Check if the sign bits of source go down as far as the truncated value.
|
|
unsigned DstTyBits = DstTy.getScalarSizeInBits();
|
|
unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
|
|
unsigned NumSrcSignBits = computeNumSignBits(Src, DemandedElts, Depth + 1);
|
|
if (NumSrcSignBits > (NumSrcBits - DstTyBits))
|
|
return NumSrcSignBits - (NumSrcBits - DstTyBits);
|
|
break;
|
|
}
|
|
case TargetOpcode::G_SELECT: {
|
|
return computeNumSignBitsMin(MI.getOperand(2).getReg(),
|
|
MI.getOperand(3).getReg(), DemandedElts,
|
|
Depth + 1);
|
|
}
|
|
case TargetOpcode::G_INTRINSIC:
|
|
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
|
|
default: {
|
|
unsigned NumBits =
|
|
TL.computeNumSignBitsForTargetInstr(*this, R, DemandedElts, MRI, Depth);
|
|
if (NumBits > 1)
|
|
FirstAnswer = std::max(FirstAnswer, NumBits);
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Finally, if we can prove that the top bits of the result are 0's or 1's,
|
|
// use this information.
|
|
KnownBits Known = getKnownBits(R, DemandedElts, Depth);
|
|
APInt Mask;
|
|
if (Known.isNonNegative()) { // sign bit is 0
|
|
Mask = Known.Zero;
|
|
} else if (Known.isNegative()) { // sign bit is 1;
|
|
Mask = Known.One;
|
|
} else {
|
|
// Nothing known.
|
|
return FirstAnswer;
|
|
}
|
|
|
|
// Okay, we know that the sign bit in Mask is set. Use CLO to determine
|
|
// the number of identical bits in the top of the input value.
|
|
Mask <<= Mask.getBitWidth() - TyBits;
|
|
return std::max(FirstAnswer, Mask.countLeadingOnes());
|
|
}
|
|
|
|
unsigned GISelKnownBits::computeNumSignBits(Register R, unsigned Depth) {
|
|
LLT Ty = MRI.getType(R);
|
|
APInt DemandedElts = Ty.isVector()
|
|
? APInt::getAllOnesValue(Ty.getNumElements())
|
|
: APInt(1, 1);
|
|
return computeNumSignBits(R, DemandedElts, Depth);
|
|
}
|
|
|
|
void GISelKnownBitsAnalysis::getAnalysisUsage(AnalysisUsage &AU) const {
|
|
AU.setPreservesAll();
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
}
|
|
|
|
bool GISelKnownBitsAnalysis::runOnMachineFunction(MachineFunction &MF) {
|
|
return false;
|
|
}
|