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154 lines
6.0 KiB
154 lines
6.0 KiB
//===- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG -*- C++ -*--==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This declares the Emit routines for the SelectionDAG class, which creates
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// MachineInstrs based on the decisions of the SelectionDAG instruction
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// selection.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H
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#define LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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namespace llvm {
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class MachineInstrBuilder;
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class MCInstrDesc;
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class SDDbgLabel;
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class SDDbgValue;
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class TargetLowering;
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class LLVM_LIBRARY_VISIBILITY InstrEmitter {
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MachineFunction *MF;
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MachineRegisterInfo *MRI;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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const TargetLowering *TLI;
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MachineBasicBlock *MBB;
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MachineBasicBlock::iterator InsertPos;
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/// Should we try to produce DBG_INSTR_REF instructions?
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bool EmitDebugInstrRefs;
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/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
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/// implicit physical register output.
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void EmitCopyFromReg(SDNode *Node, unsigned ResNo,
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bool IsClone, bool IsCloned,
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Register SrcReg,
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DenseMap<SDValue, Register> &VRBaseMap);
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void CreateVirtualRegisters(SDNode *Node,
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MachineInstrBuilder &MIB,
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const MCInstrDesc &II,
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bool IsClone, bool IsCloned,
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DenseMap<SDValue, Register> &VRBaseMap);
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/// getVR - Return the virtual register corresponding to the specified result
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/// of the specified node.
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Register getVR(SDValue Op,
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DenseMap<SDValue, Register> &VRBaseMap);
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/// AddRegisterOperand - Add the specified register as an operand to the
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/// specified machine instr. Insert register copies if the register is
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/// not in the required register class.
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void AddRegisterOperand(MachineInstrBuilder &MIB,
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SDValue Op,
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unsigned IIOpNum,
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const MCInstrDesc *II,
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DenseMap<SDValue, Register> &VRBaseMap,
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bool IsDebug, bool IsClone, bool IsCloned);
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/// AddOperand - Add the specified operand to the specified machine instr. II
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/// specifies the instruction information for the node, and IIOpNum is the
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/// operand number (in the II) that we are adding. IIOpNum and II are used for
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/// assertions only.
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void AddOperand(MachineInstrBuilder &MIB,
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SDValue Op,
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unsigned IIOpNum,
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const MCInstrDesc *II,
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DenseMap<SDValue, Register> &VRBaseMap,
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bool IsDebug, bool IsClone, bool IsCloned);
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/// ConstrainForSubReg - Try to constrain VReg to a register class that
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/// supports SubIdx sub-registers. Emit a copy if that isn't possible.
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/// Return the virtual register to use.
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Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT,
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bool isDivergent, const DebugLoc &DL);
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/// EmitSubregNode - Generate machine code for subreg nodes.
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///
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void EmitSubregNode(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap,
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bool IsClone, bool IsCloned);
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/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
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/// COPY_TO_REGCLASS is just a normal copy, except that the destination
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/// register is constrained to be in a particular register class.
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///
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void EmitCopyToRegClassNode(SDNode *Node,
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DenseMap<SDValue, Register> &VRBaseMap);
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/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
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///
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void EmitRegSequence(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap,
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bool IsClone, bool IsCloned);
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public:
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/// CountResults - The results of target nodes have register or immediate
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/// operands first, then an optional chain, and optional flag operands
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/// (which do not go into the machine instrs.)
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static unsigned CountResults(SDNode *Node);
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/// EmitDbgValue - Generate machine instruction for a dbg_value node.
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///
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MachineInstr *EmitDbgValue(SDDbgValue *SD,
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DenseMap<SDValue, Register> &VRBaseMap);
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/// Attempt to emit a dbg_value as a DBG_INSTR_REF. May fail and return
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/// nullptr, in which case we fall back to plain EmitDbgValue.
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MachineInstr *EmitDbgInstrRef(SDDbgValue *SD,
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DenseMap<SDValue, Register> &VRBaseMap);
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/// Generate machine instruction for a dbg_label node.
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MachineInstr *EmitDbgLabel(SDDbgLabel *SD);
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/// EmitNode - Generate machine code for a node and needed dependencies.
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///
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void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
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DenseMap<SDValue, Register> &VRBaseMap) {
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if (Node->isMachineOpcode())
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EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap);
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else
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EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap);
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}
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/// getBlock - Return the current basic block.
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MachineBasicBlock *getBlock() { return MBB; }
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/// getInsertPos - Return the current insertion position.
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MachineBasicBlock::iterator getInsertPos() { return InsertPos; }
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/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
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/// at the given position in the given block.
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InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb,
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MachineBasicBlock::iterator insertpos);
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private:
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void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
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DenseMap<SDValue, Register> &VRBaseMap);
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void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
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DenseMap<SDValue, Register> &VRBaseMap);
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};
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}
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#endif
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