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1053 lines
40 KiB
1053 lines
40 KiB
//===--- AArch64CallLowering.cpp - Call lowering --------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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///
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//===----------------------------------------------------------------------===//
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#include "AArch64CallLowering.h"
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#include "AArch64ISelLowering.h"
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#include "AArch64MachineFunctionInfo.h"
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#include "AArch64Subtarget.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/Argument.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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#include "llvm/Support/MachineValueType.h"
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#include <algorithm>
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#include <cassert>
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#include <cstdint>
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#include <iterator>
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#define DEBUG_TYPE "aarch64-call-lowering"
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using namespace llvm;
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AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI)
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: CallLowering(&TLI) {}
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namespace {
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struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
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IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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CCAssignFn *AssignFn)
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: IncomingValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {}
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Register getStackAddress(uint64_t Size, int64_t Offset,
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MachinePointerInfo &MPO) override {
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auto &MFI = MIRBuilder.getMF().getFrameInfo();
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int FI = MFI.CreateFixedObject(Size, Offset, true);
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MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
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auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI);
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StackUsed = std::max(StackUsed, Size + Offset);
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return AddrReg.getReg(0);
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}
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void assignValueToReg(Register ValVReg, Register PhysReg,
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CCValAssign &VA) override {
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markPhysRegUsed(PhysReg);
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switch (VA.getLocInfo()) {
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default:
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MIRBuilder.buildCopy(ValVReg, PhysReg);
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break;
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case CCValAssign::LocInfo::SExt:
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case CCValAssign::LocInfo::ZExt:
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case CCValAssign::LocInfo::AExt: {
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auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
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MIRBuilder.buildTrunc(ValVReg, Copy);
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break;
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}
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}
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}
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void assignValueToAddress(Register ValVReg, Register Addr, uint64_t MemSize,
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MachinePointerInfo &MPO, CCValAssign &VA) override {
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MachineFunction &MF = MIRBuilder.getMF();
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// The reported memory location may be wider than the value.
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const LLT RegTy = MRI.getType(ValVReg);
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MemSize = std::min(static_cast<uint64_t>(RegTy.getSizeInBytes()), MemSize);
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auto MMO = MF.getMachineMemOperand(
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MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, MemSize,
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inferAlignFromPtrInfo(MF, MPO));
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MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
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}
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/// How the physical register gets marked varies between formal
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/// parameters (it's a basic-block live-in), and a call instruction
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/// (it's an implicit-def of the BL).
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virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
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uint64_t StackUsed;
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};
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struct FormalArgHandler : public IncomingArgHandler {
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FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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CCAssignFn *AssignFn)
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: IncomingArgHandler(MIRBuilder, MRI, AssignFn) {}
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void markPhysRegUsed(MCRegister PhysReg) override {
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MIRBuilder.getMRI()->addLiveIn(PhysReg);
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MIRBuilder.getMBB().addLiveIn(PhysReg);
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}
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};
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struct CallReturnHandler : public IncomingArgHandler {
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CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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MachineInstrBuilder MIB, CCAssignFn *AssignFn)
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: IncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
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void markPhysRegUsed(MCRegister PhysReg) override {
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MIB.addDef(PhysReg, RegState::Implicit);
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}
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MachineInstrBuilder MIB;
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};
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struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
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OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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MachineInstrBuilder MIB, CCAssignFn *AssignFn,
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CCAssignFn *AssignFnVarArg, bool IsTailCall = false,
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int FPDiff = 0)
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: OutgoingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
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AssignFnVarArg(AssignFnVarArg), IsTailCall(IsTailCall), FPDiff(FPDiff),
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StackSize(0), SPReg(0) {}
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Register getStackAddress(uint64_t Size, int64_t Offset,
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MachinePointerInfo &MPO) override {
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MachineFunction &MF = MIRBuilder.getMF();
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LLT p0 = LLT::pointer(0, 64);
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LLT s64 = LLT::scalar(64);
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if (IsTailCall) {
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Offset += FPDiff;
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int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
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auto FIReg = MIRBuilder.buildFrameIndex(p0, FI);
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MPO = MachinePointerInfo::getFixedStack(MF, FI);
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return FIReg.getReg(0);
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}
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if (!SPReg)
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SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0);
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auto OffsetReg = MIRBuilder.buildConstant(s64, Offset);
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auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
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MPO = MachinePointerInfo::getStack(MF, Offset);
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return AddrReg.getReg(0);
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}
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void assignValueToReg(Register ValVReg, Register PhysReg,
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CCValAssign &VA) override {
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MIB.addUse(PhysReg, RegState::Implicit);
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Register ExtReg = extendRegister(ValVReg, VA);
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MIRBuilder.buildCopy(PhysReg, ExtReg);
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}
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void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
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MachinePointerInfo &MPO, CCValAssign &VA) override {
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MachineFunction &MF = MIRBuilder.getMF();
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auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, Size,
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inferAlignFromPtrInfo(MF, MPO));
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MIRBuilder.buildStore(ValVReg, Addr, *MMO);
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}
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void assignValueToAddress(const CallLowering::ArgInfo &Arg, Register Addr,
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uint64_t Size, MachinePointerInfo &MPO,
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CCValAssign &VA) override {
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unsigned MaxSize = Size * 8;
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// For varargs, we always want to extend them to 8 bytes, in which case
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// we disable setting a max.
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if (!Arg.IsFixed)
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MaxSize = 0;
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assert(Arg.Regs.size() == 1);
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Register ValVReg = VA.getLocInfo() != CCValAssign::LocInfo::FPExt
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? extendRegister(Arg.Regs[0], VA, MaxSize)
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: Arg.Regs[0];
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// If we extended we might need to adjust the MMO's Size.
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const LLT RegTy = MRI.getType(ValVReg);
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if (RegTy.getSizeInBytes() > Size)
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Size = RegTy.getSizeInBytes();
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assignValueToAddress(ValVReg, Addr, Size, MPO, VA);
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}
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bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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const CallLowering::ArgInfo &Info,
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ISD::ArgFlagsTy Flags,
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CCState &State) override {
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bool Res;
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if (Info.IsFixed)
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Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
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else
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Res = AssignFnVarArg(ValNo, ValVT, LocVT, LocInfo, Flags, State);
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StackSize = State.getNextStackOffset();
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return Res;
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}
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MachineInstrBuilder MIB;
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CCAssignFn *AssignFnVarArg;
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bool IsTailCall;
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/// For tail calls, the byte offset of the call's argument area from the
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/// callee's. Unused elsewhere.
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int FPDiff;
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uint64_t StackSize;
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// Cache the SP register vreg if we need it more than once in this call site.
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Register SPReg;
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};
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} // namespace
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static bool doesCalleeRestoreStack(CallingConv::ID CallConv, bool TailCallOpt) {
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return CallConv == CallingConv::Fast && TailCallOpt;
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}
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void AArch64CallLowering::splitToValueTypes(
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const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs,
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const DataLayout &DL, MachineRegisterInfo &MRI, CallingConv::ID CallConv) const {
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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LLVMContext &Ctx = OrigArg.Ty->getContext();
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SmallVector<EVT, 4> SplitVTs;
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SmallVector<uint64_t, 4> Offsets;
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ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
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if (SplitVTs.size() == 0)
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return;
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if (SplitVTs.size() == 1) {
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// No splitting to do, but we want to replace the original type (e.g. [1 x
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// double] -> double).
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SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
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OrigArg.Flags[0], OrigArg.IsFixed);
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return;
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}
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// Create one ArgInfo for each virtual register in the original ArgInfo.
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assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
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bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
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OrigArg.Ty, CallConv, false);
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for (unsigned i = 0, e = SplitVTs.size(); i < e; ++i) {
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Type *SplitTy = SplitVTs[i].getTypeForEVT(Ctx);
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SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.Flags[0],
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OrigArg.IsFixed);
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if (NeedsRegBlock)
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SplitArgs.back().Flags[0].setInConsecutiveRegs();
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}
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SplitArgs.back().Flags[0].setInConsecutiveRegsLast();
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}
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bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val,
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ArrayRef<Register> VRegs,
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Register SwiftErrorVReg) const {
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auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
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assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
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"Return value without a vreg");
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bool Success = true;
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if (!VRegs.empty()) {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = MF.getFunction();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
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auto &DL = F.getParent()->getDataLayout();
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LLVMContext &Ctx = Val->getType()->getContext();
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SmallVector<EVT, 4> SplitEVTs;
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ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
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assert(VRegs.size() == SplitEVTs.size() &&
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"For each split Type there should be exactly one VReg.");
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SmallVector<ArgInfo, 8> SplitArgs;
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CallingConv::ID CC = F.getCallingConv();
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for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
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if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) > 1) {
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LLVM_DEBUG(dbgs() << "Can't handle extended arg types which need split");
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return false;
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}
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Register CurVReg = VRegs[i];
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ArgInfo CurArgInfo = ArgInfo{CurVReg, SplitEVTs[i].getTypeForEVT(Ctx)};
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setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
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// i1 is a special case because SDAG i1 true is naturally zero extended
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// when widened using ANYEXT. We need to do it explicitly here.
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if (MRI.getType(CurVReg).getSizeInBits() == 1) {
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CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0);
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} else {
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// Some types will need extending as specified by the CC.
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MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]);
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if (EVT(NewVT) != SplitEVTs[i]) {
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unsigned ExtendOp = TargetOpcode::G_ANYEXT;
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if (F.getAttributes().hasAttribute(AttributeList::ReturnIndex,
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Attribute::SExt))
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ExtendOp = TargetOpcode::G_SEXT;
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else if (F.getAttributes().hasAttribute(AttributeList::ReturnIndex,
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Attribute::ZExt))
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ExtendOp = TargetOpcode::G_ZEXT;
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LLT NewLLT(NewVT);
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LLT OldLLT(MVT::getVT(CurArgInfo.Ty));
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CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx);
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// Instead of an extend, we might have a vector type which needs
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// padding with more elements, e.g. <2 x half> -> <4 x half>.
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if (NewVT.isVector()) {
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if (OldLLT.isVector()) {
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if (NewLLT.getNumElements() > OldLLT.getNumElements()) {
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// We don't handle VA types which are not exactly twice the
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// size, but can easily be done in future.
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if (NewLLT.getNumElements() != OldLLT.getNumElements() * 2) {
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LLVM_DEBUG(dbgs() << "Outgoing vector ret has too many elts");
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return false;
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}
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auto Undef = MIRBuilder.buildUndef({OldLLT});
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CurVReg =
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MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef}).getReg(0);
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} else {
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// Just do a vector extend.
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CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
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.getReg(0);
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}
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} else if (NewLLT.getNumElements() == 2) {
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// We need to pad a <1 x S> type to <2 x S>. Since we don't have
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// <1 x S> vector types in GISel we use a build_vector instead
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// of a vector merge/concat.
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auto Undef = MIRBuilder.buildUndef({OldLLT});
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CurVReg =
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MIRBuilder
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.buildBuildVector({NewLLT}, {CurVReg, Undef.getReg(0)})
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.getReg(0);
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} else {
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LLVM_DEBUG(dbgs() << "Could not handle ret ty");
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return false;
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}
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} else {
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// A scalar extend.
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CurVReg =
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MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}).getReg(0);
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}
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}
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}
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if (CurVReg != CurArgInfo.Regs[0]) {
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CurArgInfo.Regs[0] = CurVReg;
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// Reset the arg flags after modifying CurVReg.
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setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
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}
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splitToValueTypes(CurArgInfo, SplitArgs, DL, MRI, CC);
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}
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OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn);
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Success = handleAssignments(MIRBuilder, SplitArgs, Handler);
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}
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if (SwiftErrorVReg) {
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MIB.addUse(AArch64::X21, RegState::Implicit);
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MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg);
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}
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MIRBuilder.insertInstr(MIB);
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return Success;
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}
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/// Helper function to compute forwarded registers for musttail calls. Computes
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/// the forwarded registers, sets MBB liveness, and emits COPY instructions that
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/// can be used to save + restore registers later.
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static void handleMustTailForwardedRegisters(MachineIRBuilder &MIRBuilder,
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CCAssignFn *AssignFn) {
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MachineBasicBlock &MBB = MIRBuilder.getMBB();
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MachineFunction &MF = MIRBuilder.getMF();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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if (!MFI.hasMustTailInVarArgFunc())
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return;
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AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
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const Function &F = MF.getFunction();
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assert(F.isVarArg() && "Expected F to be vararg?");
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// Compute the set of forwarded registers. The rest are scratch.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(F.getCallingConv(), /*IsVarArg=*/true, MF, ArgLocs,
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F.getContext());
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SmallVector<MVT, 2> RegParmTypes;
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RegParmTypes.push_back(MVT::i64);
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RegParmTypes.push_back(MVT::f128);
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// Later on, we can use this vector to restore the registers if necessary.
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SmallVectorImpl<ForwardedRegister> &Forwards =
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FuncInfo->getForwardedMustTailRegParms();
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CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, AssignFn);
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// Conservatively forward X8, since it might be used for an aggregate
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// return.
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if (!CCInfo.isAllocated(AArch64::X8)) {
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Register X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass);
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Forwards.push_back(ForwardedRegister(X8VReg, AArch64::X8, MVT::i64));
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}
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// Add the forwards to the MachineBasicBlock and MachineFunction.
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for (const auto &F : Forwards) {
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MBB.addLiveIn(F.PReg);
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MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg));
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}
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}
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bool AArch64CallLowering::fallBackToDAGISel(const Function &F) const {
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if (isa<ScalableVectorType>(F.getReturnType()))
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return true;
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return llvm::any_of(F.args(), [](const Argument &A) {
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return isa<ScalableVectorType>(A.getType());
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});
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}
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bool AArch64CallLowering::lowerFormalArguments(
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MachineIRBuilder &MIRBuilder, const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs) const {
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MachineFunction &MF = MIRBuilder.getMF();
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MachineBasicBlock &MBB = MIRBuilder.getMBB();
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
auto &DL = F.getParent()->getDataLayout();
|
|
|
|
SmallVector<ArgInfo, 8> SplitArgs;
|
|
unsigned i = 0;
|
|
for (auto &Arg : F.args()) {
|
|
if (DL.getTypeStoreSize(Arg.getType()).isZero())
|
|
continue;
|
|
|
|
ArgInfo OrigArg{VRegs[i], Arg.getType()};
|
|
setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F);
|
|
|
|
splitToValueTypes(OrigArg, SplitArgs, DL, MRI, F.getCallingConv());
|
|
++i;
|
|
}
|
|
|
|
if (!MBB.empty())
|
|
MIRBuilder.setInstr(*MBB.begin());
|
|
|
|
const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
|
|
CCAssignFn *AssignFn =
|
|
TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
|
|
|
|
FormalArgHandler Handler(MIRBuilder, MRI, AssignFn);
|
|
if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
|
|
return false;
|
|
|
|
AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
|
|
uint64_t StackOffset = Handler.StackUsed;
|
|
if (F.isVarArg()) {
|
|
auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
|
|
if (!Subtarget.isTargetDarwin()) {
|
|
// FIXME: we need to reimplement saveVarArgsRegisters from
|
|
// AArch64ISelLowering.
|
|
return false;
|
|
}
|
|
|
|
// We currently pass all varargs at 8-byte alignment, or 4 in ILP32.
|
|
StackOffset = alignTo(Handler.StackUsed, Subtarget.isTargetILP32() ? 4 : 8);
|
|
|
|
auto &MFI = MIRBuilder.getMF().getFrameInfo();
|
|
FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));
|
|
}
|
|
|
|
if (doesCalleeRestoreStack(F.getCallingConv(),
|
|
MF.getTarget().Options.GuaranteedTailCallOpt)) {
|
|
// We have a non-standard ABI, so why not make full use of the stack that
|
|
// we're going to pop? It must be aligned to 16 B in any case.
|
|
StackOffset = alignTo(StackOffset, 16);
|
|
|
|
// If we're expected to restore the stack (e.g. fastcc), then we'll be
|
|
// adding a multiple of 16.
|
|
FuncInfo->setArgumentStackToRestore(StackOffset);
|
|
|
|
// Our own callers will guarantee that the space is free by giving an
|
|
// aligned value to CALLSEQ_START.
|
|
}
|
|
|
|
// When we tail call, we need to check if the callee's arguments
|
|
// will fit on the caller's stack. So, whenever we lower formal arguments,
|
|
// we should keep track of this information, since we might lower a tail call
|
|
// in this function later.
|
|
FuncInfo->setBytesInStackArgArea(StackOffset);
|
|
|
|
auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
|
|
if (Subtarget.hasCustomCallingConv())
|
|
Subtarget.getRegisterInfo()->UpdateCustomCalleeSavedRegs(MF);
|
|
|
|
handleMustTailForwardedRegisters(MIRBuilder, AssignFn);
|
|
|
|
// Move back to the end of the basic block.
|
|
MIRBuilder.setMBB(MBB);
|
|
|
|
return true;
|
|
}
|
|
|
|
/// Return true if the calling convention is one that we can guarantee TCO for.
|
|
static bool canGuaranteeTCO(CallingConv::ID CC) {
|
|
return CC == CallingConv::Fast;
|
|
}
|
|
|
|
/// Return true if we might ever do TCO for calls with this calling convention.
|
|
static bool mayTailCallThisCC(CallingConv::ID CC) {
|
|
switch (CC) {
|
|
case CallingConv::C:
|
|
case CallingConv::PreserveMost:
|
|
case CallingConv::Swift:
|
|
return true;
|
|
default:
|
|
return canGuaranteeTCO(CC);
|
|
}
|
|
}
|
|
|
|
/// Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for
|
|
/// CC.
|
|
static std::pair<CCAssignFn *, CCAssignFn *>
|
|
getAssignFnsForCC(CallingConv::ID CC, const AArch64TargetLowering &TLI) {
|
|
return {TLI.CCAssignFnForCall(CC, false), TLI.CCAssignFnForCall(CC, true)};
|
|
}
|
|
|
|
bool AArch64CallLowering::doCallerAndCalleePassArgsTheSameWay(
|
|
CallLoweringInfo &Info, MachineFunction &MF,
|
|
SmallVectorImpl<ArgInfo> &InArgs) const {
|
|
const Function &CallerF = MF.getFunction();
|
|
CallingConv::ID CalleeCC = Info.CallConv;
|
|
CallingConv::ID CallerCC = CallerF.getCallingConv();
|
|
|
|
// If the calling conventions match, then everything must be the same.
|
|
if (CalleeCC == CallerCC)
|
|
return true;
|
|
|
|
// Check if the caller and callee will handle arguments in the same way.
|
|
const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
|
|
CCAssignFn *CalleeAssignFnFixed;
|
|
CCAssignFn *CalleeAssignFnVarArg;
|
|
std::tie(CalleeAssignFnFixed, CalleeAssignFnVarArg) =
|
|
getAssignFnsForCC(CalleeCC, TLI);
|
|
|
|
CCAssignFn *CallerAssignFnFixed;
|
|
CCAssignFn *CallerAssignFnVarArg;
|
|
std::tie(CallerAssignFnFixed, CallerAssignFnVarArg) =
|
|
getAssignFnsForCC(CallerCC, TLI);
|
|
|
|
if (!resultsCompatible(Info, MF, InArgs, *CalleeAssignFnFixed,
|
|
*CalleeAssignFnVarArg, *CallerAssignFnFixed,
|
|
*CallerAssignFnVarArg))
|
|
return false;
|
|
|
|
// Make sure that the caller and callee preserve all of the same registers.
|
|
auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
|
|
const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
|
|
const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
|
|
if (MF.getSubtarget<AArch64Subtarget>().hasCustomCallingConv()) {
|
|
TRI->UpdateCustomCallPreservedMask(MF, &CallerPreserved);
|
|
TRI->UpdateCustomCallPreservedMask(MF, &CalleePreserved);
|
|
}
|
|
|
|
return TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved);
|
|
}
|
|
|
|
bool AArch64CallLowering::areCalleeOutgoingArgsTailCallable(
|
|
CallLoweringInfo &Info, MachineFunction &MF,
|
|
SmallVectorImpl<ArgInfo> &OutArgs) const {
|
|
// If there are no outgoing arguments, then we are done.
|
|
if (OutArgs.empty())
|
|
return true;
|
|
|
|
const Function &CallerF = MF.getFunction();
|
|
CallingConv::ID CalleeCC = Info.CallConv;
|
|
CallingConv::ID CallerCC = CallerF.getCallingConv();
|
|
const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
|
|
|
|
CCAssignFn *AssignFnFixed;
|
|
CCAssignFn *AssignFnVarArg;
|
|
std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
|
|
|
|
// We have outgoing arguments. Make sure that we can tail call with them.
|
|
SmallVector<CCValAssign, 16> OutLocs;
|
|
CCState OutInfo(CalleeCC, false, MF, OutLocs, CallerF.getContext());
|
|
|
|
if (!analyzeArgInfo(OutInfo, OutArgs, *AssignFnFixed, *AssignFnVarArg)) {
|
|
LLVM_DEBUG(dbgs() << "... Could not analyze call operands.\n");
|
|
return false;
|
|
}
|
|
|
|
// Make sure that they can fit on the caller's stack.
|
|
const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
|
|
if (OutInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea()) {
|
|
LLVM_DEBUG(dbgs() << "... Cannot fit call operands on caller's stack.\n");
|
|
return false;
|
|
}
|
|
|
|
// Verify that the parameters in callee-saved registers match.
|
|
// TODO: Port this over to CallLowering as general code once swiftself is
|
|
// supported.
|
|
auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
|
|
const uint32_t *CallerPreservedMask = TRI->getCallPreservedMask(MF, CallerCC);
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
for (unsigned i = 0; i < OutLocs.size(); ++i) {
|
|
auto &ArgLoc = OutLocs[i];
|
|
// If it's not a register, it's fine.
|
|
if (!ArgLoc.isRegLoc()) {
|
|
if (Info.IsVarArg) {
|
|
// Be conservative and disallow variadic memory operands to match SDAG's
|
|
// behaviour.
|
|
// FIXME: If the caller's calling convention is C, then we can
|
|
// potentially use its argument area. However, for cases like fastcc,
|
|
// we can't do anything.
|
|
LLVM_DEBUG(
|
|
dbgs()
|
|
<< "... Cannot tail call vararg function with stack arguments\n");
|
|
return false;
|
|
}
|
|
continue;
|
|
}
|
|
|
|
Register Reg = ArgLoc.getLocReg();
|
|
|
|
// Only look at callee-saved registers.
|
|
if (MachineOperand::clobbersPhysReg(CallerPreservedMask, Reg))
|
|
continue;
|
|
|
|
LLVM_DEBUG(
|
|
dbgs()
|
|
<< "... Call has an argument passed in a callee-saved register.\n");
|
|
|
|
// Check if it was copied from.
|
|
ArgInfo &OutInfo = OutArgs[i];
|
|
|
|
if (OutInfo.Regs.size() > 1) {
|
|
LLVM_DEBUG(
|
|
dbgs() << "... Cannot handle arguments in multiple registers.\n");
|
|
return false;
|
|
}
|
|
|
|
// Check if we copy the register, walking through copies from virtual
|
|
// registers. Note that getDefIgnoringCopies does not ignore copies from
|
|
// physical registers.
|
|
MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI);
|
|
if (!RegDef || RegDef->getOpcode() != TargetOpcode::COPY) {
|
|
LLVM_DEBUG(
|
|
dbgs()
|
|
<< "... Parameter was not copied into a VReg, cannot tail call.\n");
|
|
return false;
|
|
}
|
|
|
|
// Got a copy. Verify that it's the same as the register we want.
|
|
Register CopyRHS = RegDef->getOperand(1).getReg();
|
|
if (CopyRHS != Reg) {
|
|
LLVM_DEBUG(dbgs() << "... Callee-saved register was not copied into "
|
|
"VReg, cannot tail call.\n");
|
|
return false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool AArch64CallLowering::isEligibleForTailCallOptimization(
|
|
MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
|
|
SmallVectorImpl<ArgInfo> &InArgs,
|
|
SmallVectorImpl<ArgInfo> &OutArgs) const {
|
|
|
|
// Must pass all target-independent checks in order to tail call optimize.
|
|
if (!Info.IsTailCall)
|
|
return false;
|
|
|
|
CallingConv::ID CalleeCC = Info.CallConv;
|
|
MachineFunction &MF = MIRBuilder.getMF();
|
|
const Function &CallerF = MF.getFunction();
|
|
|
|
LLVM_DEBUG(dbgs() << "Attempting to lower call as tail call\n");
|
|
|
|
if (Info.SwiftErrorVReg) {
|
|
// TODO: We should handle this.
|
|
// Note that this is also handled by the check for no outgoing arguments.
|
|
// Proactively disabling this though, because the swifterror handling in
|
|
// lowerCall inserts a COPY *after* the location of the call.
|
|
LLVM_DEBUG(dbgs() << "... Cannot handle tail calls with swifterror yet.\n");
|
|
return false;
|
|
}
|
|
|
|
if (!mayTailCallThisCC(CalleeCC)) {
|
|
LLVM_DEBUG(dbgs() << "... Calling convention cannot be tail called.\n");
|
|
return false;
|
|
}
|
|
|
|
// Byval parameters hand the function a pointer directly into the stack area
|
|
// we want to reuse during a tail call. Working around this *is* possible (see
|
|
// X86).
|
|
//
|
|
// FIXME: In AArch64ISelLowering, this isn't worked around. Can/should we try
|
|
// it?
|
|
//
|
|
// On Windows, "inreg" attributes signify non-aggregate indirect returns.
|
|
// In this case, it is necessary to save/restore X0 in the callee. Tail
|
|
// call opt interferes with this. So we disable tail call opt when the
|
|
// caller has an argument with "inreg" attribute.
|
|
//
|
|
// FIXME: Check whether the callee also has an "inreg" argument.
|
|
//
|
|
// When the caller has a swifterror argument, we don't want to tail call
|
|
// because would have to move into the swifterror register before the
|
|
// tail call.
|
|
if (any_of(CallerF.args(), [](const Argument &A) {
|
|
return A.hasByValAttr() || A.hasInRegAttr() || A.hasSwiftErrorAttr();
|
|
})) {
|
|
LLVM_DEBUG(dbgs() << "... Cannot tail call from callers with byval, "
|
|
"inreg, or swifterror arguments\n");
|
|
return false;
|
|
}
|
|
|
|
// Externally-defined functions with weak linkage should not be
|
|
// tail-called on AArch64 when the OS does not support dynamic
|
|
// pre-emption of symbols, as the AAELF spec requires normal calls
|
|
// to undefined weak functions to be replaced with a NOP or jump to the
|
|
// next instruction. The behaviour of branch instructions in this
|
|
// situation (as used for tail calls) is implementation-defined, so we
|
|
// cannot rely on the linker replacing the tail call with a return.
|
|
if (Info.Callee.isGlobal()) {
|
|
const GlobalValue *GV = Info.Callee.getGlobal();
|
|
const Triple &TT = MF.getTarget().getTargetTriple();
|
|
if (GV->hasExternalWeakLinkage() &&
|
|
(!TT.isOSWindows() || TT.isOSBinFormatELF() ||
|
|
TT.isOSBinFormatMachO())) {
|
|
LLVM_DEBUG(dbgs() << "... Cannot tail call externally-defined function "
|
|
"with weak linkage for this OS.\n");
|
|
return false;
|
|
}
|
|
}
|
|
|
|
// If we have -tailcallopt, then we're done.
|
|
if (MF.getTarget().Options.GuaranteedTailCallOpt)
|
|
return canGuaranteeTCO(CalleeCC) && CalleeCC == CallerF.getCallingConv();
|
|
|
|
// We don't have -tailcallopt, so we're allowed to change the ABI (sibcall).
|
|
// Try to find cases where we can do that.
|
|
|
|
// I want anyone implementing a new calling convention to think long and hard
|
|
// about this assert.
|
|
assert((!Info.IsVarArg || CalleeCC == CallingConv::C) &&
|
|
"Unexpected variadic calling convention");
|
|
|
|
// Verify that the incoming and outgoing arguments from the callee are
|
|
// safe to tail call.
|
|
if (!doCallerAndCalleePassArgsTheSameWay(Info, MF, InArgs)) {
|
|
LLVM_DEBUG(
|
|
dbgs()
|
|
<< "... Caller and callee have incompatible calling conventions.\n");
|
|
return false;
|
|
}
|
|
|
|
if (!areCalleeOutgoingArgsTailCallable(Info, MF, OutArgs))
|
|
return false;
|
|
|
|
LLVM_DEBUG(
|
|
dbgs() << "... Call is eligible for tail call optimization.\n");
|
|
return true;
|
|
}
|
|
|
|
static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect,
|
|
bool IsTailCall) {
|
|
if (!IsTailCall)
|
|
return IsIndirect ? getBLRCallOpcode(CallerF) : (unsigned)AArch64::BL;
|
|
|
|
if (!IsIndirect)
|
|
return AArch64::TCRETURNdi;
|
|
|
|
// When BTI is enabled, we need to use TCRETURNriBTI to make sure that we use
|
|
// x16 or x17.
|
|
if (CallerF.getInfo<AArch64FunctionInfo>()->branchTargetEnforcement())
|
|
return AArch64::TCRETURNriBTI;
|
|
|
|
return AArch64::TCRETURNri;
|
|
}
|
|
|
|
bool AArch64CallLowering::lowerTailCall(
|
|
MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
|
|
SmallVectorImpl<ArgInfo> &OutArgs) const {
|
|
MachineFunction &MF = MIRBuilder.getMF();
|
|
const Function &F = MF.getFunction();
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
|
|
AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
|
|
|
|
// True when we're tail calling, but without -tailcallopt.
|
|
bool IsSibCall = !MF.getTarget().Options.GuaranteedTailCallOpt;
|
|
|
|
// TODO: Right now, regbankselect doesn't know how to handle the rtcGPR64
|
|
// register class. Until we can do that, we should fall back here.
|
|
if (MF.getInfo<AArch64FunctionInfo>()->branchTargetEnforcement()) {
|
|
LLVM_DEBUG(
|
|
dbgs() << "Cannot lower indirect tail calls with BTI enabled yet.\n");
|
|
return false;
|
|
}
|
|
|
|
// Find out which ABI gets to decide where things go.
|
|
CallingConv::ID CalleeCC = Info.CallConv;
|
|
CCAssignFn *AssignFnFixed;
|
|
CCAssignFn *AssignFnVarArg;
|
|
std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
|
|
|
|
MachineInstrBuilder CallSeqStart;
|
|
if (!IsSibCall)
|
|
CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
|
|
|
|
unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), true);
|
|
auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
|
|
MIB.add(Info.Callee);
|
|
|
|
// Byte offset for the tail call. When we are sibcalling, this will always
|
|
// be 0.
|
|
MIB.addImm(0);
|
|
|
|
// Tell the call which registers are clobbered.
|
|
auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
|
|
const uint32_t *Mask = TRI->getCallPreservedMask(MF, CalleeCC);
|
|
if (MF.getSubtarget<AArch64Subtarget>().hasCustomCallingConv())
|
|
TRI->UpdateCustomCallPreservedMask(MF, &Mask);
|
|
MIB.addRegMask(Mask);
|
|
|
|
if (TRI->isAnyArgRegReserved(MF))
|
|
TRI->emitReservedArgRegCallError(MF);
|
|
|
|
// FPDiff is the byte offset of the call's argument area from the callee's.
|
|
// Stores to callee stack arguments will be placed in FixedStackSlots offset
|
|
// by this amount for a tail call. In a sibling call it must be 0 because the
|
|
// caller will deallocate the entire stack and the callee still expects its
|
|
// arguments to begin at SP+0.
|
|
int FPDiff = 0;
|
|
|
|
// This will be 0 for sibcalls, potentially nonzero for tail calls produced
|
|
// by -tailcallopt. For sibcalls, the memory operands for the call are
|
|
// already available in the caller's incoming argument space.
|
|
unsigned NumBytes = 0;
|
|
if (!IsSibCall) {
|
|
// We aren't sibcalling, so we need to compute FPDiff. We need to do this
|
|
// before handling assignments, because FPDiff must be known for memory
|
|
// arguments.
|
|
unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
|
|
SmallVector<CCValAssign, 16> OutLocs;
|
|
CCState OutInfo(CalleeCC, false, MF, OutLocs, F.getContext());
|
|
analyzeArgInfo(OutInfo, OutArgs, *AssignFnFixed, *AssignFnVarArg);
|
|
|
|
// The callee will pop the argument stack as a tail call. Thus, we must
|
|
// keep it 16-byte aligned.
|
|
NumBytes = alignTo(OutInfo.getNextStackOffset(), 16);
|
|
|
|
// FPDiff will be negative if this tail call requires more space than we
|
|
// would automatically have in our incoming argument space. Positive if we
|
|
// actually shrink the stack.
|
|
FPDiff = NumReusableBytes - NumBytes;
|
|
|
|
// The stack pointer must be 16-byte aligned at all times it's used for a
|
|
// memory operation, which in practice means at *all* times and in
|
|
// particular across call boundaries. Therefore our own arguments started at
|
|
// a 16-byte aligned SP and the delta applied for the tail call should
|
|
// satisfy the same constraint.
|
|
assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
|
|
}
|
|
|
|
const auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
|
|
|
|
// Do the actual argument marshalling.
|
|
OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
|
|
AssignFnVarArg, true, FPDiff);
|
|
if (!handleAssignments(MIRBuilder, OutArgs, Handler))
|
|
return false;
|
|
|
|
if (Info.IsVarArg && Info.IsMustTailCall) {
|
|
// Now we know what's being passed to the function. Add uses to the call for
|
|
// the forwarded registers that we *aren't* passing as parameters. This will
|
|
// preserve the copies we build earlier.
|
|
for (const auto &F : Forwards) {
|
|
Register ForwardedReg = F.PReg;
|
|
// If the register is already passed, or aliases a register which is
|
|
// already being passed, then skip it.
|
|
if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) {
|
|
if (!Use.isReg())
|
|
return false;
|
|
return TRI->regsOverlap(Use.getReg(), ForwardedReg);
|
|
}))
|
|
continue;
|
|
|
|
// We aren't passing it already, so we should add it to the call.
|
|
MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg));
|
|
MIB.addReg(ForwardedReg, RegState::Implicit);
|
|
}
|
|
}
|
|
|
|
// If we have -tailcallopt, we need to adjust the stack. We'll do the call
|
|
// sequence start and end here.
|
|
if (!IsSibCall) {
|
|
MIB->getOperand(1).setImm(FPDiff);
|
|
CallSeqStart.addImm(NumBytes).addImm(0);
|
|
// End the call sequence *before* emitting the call. Normally, we would
|
|
// tidy the frame up after the call. However, here, we've laid out the
|
|
// parameters so that when SP is reset, they will be in the correct
|
|
// location.
|
|
MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(NumBytes).addImm(0);
|
|
}
|
|
|
|
// Now we can add the actual call instruction to the correct basic block.
|
|
MIRBuilder.insertInstr(MIB);
|
|
|
|
// If Callee is a reg, since it is used by a target specific instruction,
|
|
// it must have a register class matching the constraint of that instruction.
|
|
if (Info.Callee.isReg())
|
|
MIB->getOperand(0).setReg(constrainOperandRegClass(
|
|
MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
|
|
*MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
|
|
0));
|
|
|
|
MF.getFrameInfo().setHasTailCall();
|
|
Info.LoweredTailCall = true;
|
|
return true;
|
|
}
|
|
|
|
bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
|
|
CallLoweringInfo &Info) const {
|
|
MachineFunction &MF = MIRBuilder.getMF();
|
|
const Function &F = MF.getFunction();
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
auto &DL = F.getParent()->getDataLayout();
|
|
const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
|
|
|
|
SmallVector<ArgInfo, 8> OutArgs;
|
|
for (auto &OrigArg : Info.OrigArgs) {
|
|
splitToValueTypes(OrigArg, OutArgs, DL, MRI, Info.CallConv);
|
|
// AAPCS requires that we zero-extend i1 to 8 bits by the caller.
|
|
if (OrigArg.Ty->isIntegerTy(1))
|
|
OutArgs.back().Flags[0].setZExt();
|
|
}
|
|
|
|
SmallVector<ArgInfo, 8> InArgs;
|
|
if (!Info.OrigRet.Ty->isVoidTy())
|
|
splitToValueTypes(Info.OrigRet, InArgs, DL, MRI, F.getCallingConv());
|
|
|
|
// If we can lower as a tail call, do that instead.
|
|
bool CanTailCallOpt =
|
|
isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs);
|
|
|
|
// We must emit a tail call if we have musttail.
|
|
if (Info.IsMustTailCall && !CanTailCallOpt) {
|
|
// There are types of incoming/outgoing arguments we can't handle yet, so
|
|
// it doesn't make sense to actually die here like in ISelLowering. Instead,
|
|
// fall back to SelectionDAG and let it try to handle this.
|
|
LLVM_DEBUG(dbgs() << "Failed to lower musttail call as tail call\n");
|
|
return false;
|
|
}
|
|
|
|
if (CanTailCallOpt)
|
|
return lowerTailCall(MIRBuilder, Info, OutArgs);
|
|
|
|
// Find out which ABI gets to decide where things go.
|
|
CCAssignFn *AssignFnFixed;
|
|
CCAssignFn *AssignFnVarArg;
|
|
std::tie(AssignFnFixed, AssignFnVarArg) =
|
|
getAssignFnsForCC(Info.CallConv, TLI);
|
|
|
|
MachineInstrBuilder CallSeqStart;
|
|
CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
|
|
|
|
// Create a temporarily-floating call instruction so we can add the implicit
|
|
// uses of arg registers.
|
|
unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), false);
|
|
|
|
auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
|
|
MIB.add(Info.Callee);
|
|
|
|
// Tell the call which registers are clobbered.
|
|
auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
|
|
const uint32_t *Mask = TRI->getCallPreservedMask(MF, Info.CallConv);
|
|
if (MF.getSubtarget<AArch64Subtarget>().hasCustomCallingConv())
|
|
TRI->UpdateCustomCallPreservedMask(MF, &Mask);
|
|
MIB.addRegMask(Mask);
|
|
|
|
if (TRI->isAnyArgRegReserved(MF))
|
|
TRI->emitReservedArgRegCallError(MF);
|
|
|
|
// Do the actual argument marshalling.
|
|
OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
|
|
AssignFnVarArg, false);
|
|
if (!handleAssignments(MIRBuilder, OutArgs, Handler))
|
|
return false;
|
|
|
|
// Now we can add the actual call instruction to the correct basic block.
|
|
MIRBuilder.insertInstr(MIB);
|
|
|
|
// If Callee is a reg, since it is used by a target specific
|
|
// instruction, it must have a register class matching the
|
|
// constraint of that instruction.
|
|
if (Info.Callee.isReg())
|
|
MIB->getOperand(0).setReg(constrainOperandRegClass(
|
|
MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
|
|
*MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
|
|
0));
|
|
|
|
// Finally we can copy the returned value back into its virtual-register. In
|
|
// symmetry with the arguments, the physical register must be an
|
|
// implicit-define of the call instruction.
|
|
if (!Info.OrigRet.Ty->isVoidTy()) {
|
|
CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv);
|
|
CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn);
|
|
if (!handleAssignments(MIRBuilder, InArgs, Handler))
|
|
return false;
|
|
}
|
|
|
|
if (Info.SwiftErrorVReg) {
|
|
MIB.addDef(AArch64::X21, RegState::Implicit);
|
|
MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));
|
|
}
|
|
|
|
uint64_t CalleePopBytes =
|
|
doesCalleeRestoreStack(Info.CallConv,
|
|
MF.getTarget().Options.GuaranteedTailCallOpt)
|
|
? alignTo(Handler.StackSize, 16)
|
|
: 0;
|
|
|
|
CallSeqStart.addImm(Handler.StackSize).addImm(0);
|
|
MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
|
|
.addImm(Handler.StackSize)
|
|
.addImm(CalleePopBytes);
|
|
|
|
return true;
|
|
}
|