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94 lines
3.2 KiB
94 lines
3.2 KiB
//===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// This file contains declaration for AMDGPU ISA disassembler
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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namespace llvm {
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class MCContext;
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class MCInst;
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class MCOperand;
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class MCSubtargetInfo;
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class Twine;
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class AMDGPUDisassembler : public MCDisassembler {
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private:
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mutable ArrayRef<uint8_t> Bytes;
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public:
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AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
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MCDisassembler(STI, Ctx) {}
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~AMDGPUDisassembler() {}
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DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &WS, raw_ostream &CS) const override;
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const char* getRegClassName(unsigned RegClassID) const;
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MCOperand createRegOperand(unsigned int RegId) const;
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MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
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MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
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MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const;
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DecodeStatus tryDecodeInst(const uint8_t* Table,
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MCInst &MI,
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uint64_t Inst,
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uint64_t Address) const;
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MCOperand decodeOperand_VGPR_32(unsigned Val) const;
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MCOperand decodeOperand_VS_32(unsigned Val) const;
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MCOperand decodeOperand_VS_64(unsigned Val) const;
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MCOperand decodeOperand_VReg_64(unsigned Val) const;
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MCOperand decodeOperand_VReg_96(unsigned Val) const;
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MCOperand decodeOperand_VReg_128(unsigned Val) const;
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MCOperand decodeOperand_SReg_32(unsigned Val) const;
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MCOperand decodeOperand_SReg_32_XM0(unsigned Val) const;
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MCOperand decodeOperand_SReg_64(unsigned Val) const;
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MCOperand decodeOperand_SReg_128(unsigned Val) const;
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MCOperand decodeOperand_SReg_256(unsigned Val) const;
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MCOperand decodeOperand_SReg_512(unsigned Val) const;
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enum OpWidthTy {
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OPW32,
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OPW64,
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OPW128,
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OPW_LAST_,
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OPW_FIRST_ = OPW32
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};
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unsigned getVgprClassId(const OpWidthTy Width) const;
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unsigned getSgprClassId(const OpWidthTy Width) const;
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unsigned getTtmpClassId(const OpWidthTy Width) const;
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static MCOperand decodeIntImmed(unsigned Imm);
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static MCOperand decodeFPImmed(bool Is32, unsigned Imm);
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MCOperand decodeLiteralConstant() const;
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MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
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MCOperand decodeSpecialReg32(unsigned Val) const;
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MCOperand decodeSpecialReg64(unsigned Val) const;
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};
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} // namespace llvm
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#endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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