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91 lines
2.6 KiB
91 lines
2.6 KiB
//===-- SIFixControlFlowLiveIntervals.cpp - Fix CF live intervals ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Spilling of EXEC masks used for control flow messes up control flow
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/// lowering, so mark all live intervals associated with CF instructions as
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/// non-spillable.
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///
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "si-fix-cf-live-intervals"
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namespace {
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class SIFixControlFlowLiveIntervals : public MachineFunctionPass {
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public:
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static char ID;
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public:
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SIFixControlFlowLiveIntervals() : MachineFunctionPass(ID) {
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initializeSIFixControlFlowLiveIntervalsPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "SI Fix CF Live Intervals";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<LiveIntervals>();
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(SIFixControlFlowLiveIntervals, DEBUG_TYPE,
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"SI Fix CF Live Intervals", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_END(SIFixControlFlowLiveIntervals, DEBUG_TYPE,
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"SI Fix CF Live Intervals", false, false)
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char SIFixControlFlowLiveIntervals::ID = 0;
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char &llvm::SIFixControlFlowLiveIntervalsID = SIFixControlFlowLiveIntervals::ID;
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FunctionPass *llvm::createSIFixControlFlowLiveIntervalsPass() {
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return new SIFixControlFlowLiveIntervals();
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}
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bool SIFixControlFlowLiveIntervals::runOnMachineFunction(MachineFunction &MF) {
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LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
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for (const MachineBasicBlock &MBB : MF) {
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for (const MachineInstr &MI : MBB) {
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switch (MI.getOpcode()) {
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case AMDGPU::SI_IF:
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case AMDGPU::SI_ELSE:
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case AMDGPU::SI_BREAK:
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case AMDGPU::SI_IF_BREAK:
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case AMDGPU::SI_ELSE_BREAK:
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case AMDGPU::SI_END_CF: {
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unsigned Reg = MI.getOperand(0).getReg();
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LIS->getInterval(Reg).markNotSpillable();
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break;
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}
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default:
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break;
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}
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}
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}
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return false;
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}
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