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411 lines
14 KiB
411 lines
14 KiB
//===-- SIShrinkInstructions.cpp - Shrink Instructions --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// The pass tries to use the 32-bit encoding for instructions when possible.
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//===----------------------------------------------------------------------===//
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//
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#include "AMDGPU.h"
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#include "AMDGPUMCInstLower.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#define DEBUG_TYPE "si-shrink-instructions"
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STATISTIC(NumInstructionsShrunk,
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"Number of 64-bit instruction reduced to 32-bit.");
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STATISTIC(NumLiteralConstantsFolded,
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"Number of literal constants folded into 32-bit instructions.");
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using namespace llvm;
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namespace {
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class SIShrinkInstructions : public MachineFunctionPass {
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public:
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static char ID;
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public:
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SIShrinkInstructions() : MachineFunctionPass(ID) {
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "SI Shrink Instructions";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS(SIShrinkInstructions, DEBUG_TYPE,
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"SI Shrink Instructions", false, false)
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char SIShrinkInstructions::ID = 0;
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FunctionPass *llvm::createSIShrinkInstructionsPass() {
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return new SIShrinkInstructions();
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}
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static bool isVGPR(const MachineOperand *MO, const SIRegisterInfo &TRI,
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const MachineRegisterInfo &MRI) {
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if (!MO->isReg())
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return false;
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if (TargetRegisterInfo::isVirtualRegister(MO->getReg()))
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return TRI.hasVGPRs(MRI.getRegClass(MO->getReg()));
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return TRI.hasVGPRs(TRI.getPhysRegClass(MO->getReg()));
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}
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static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII,
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const SIRegisterInfo &TRI,
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const MachineRegisterInfo &MRI) {
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const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
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// Can't shrink instruction with three operands.
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// FIXME: v_cndmask_b32 has 3 operands and is shrinkable, but we need to add
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// a special case for it. It can only be shrunk if the third operand
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// is vcc. We should handle this the same way we handle vopc, by addding
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// a register allocation hint pre-regalloc and then do the shrining
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// post-regalloc.
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if (Src2) {
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switch (MI.getOpcode()) {
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default: return false;
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case AMDGPU::V_MAC_F32_e64:
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if (!isVGPR(Src2, TRI, MRI) ||
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TII->hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))
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return false;
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break;
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case AMDGPU::V_CNDMASK_B32_e64:
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break;
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}
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}
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const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
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const MachineOperand *Src1Mod =
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TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
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if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0)))
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return false;
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// We don't need to check src0, all input types are legal, so just make sure
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// src0 isn't using any modifiers.
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if (TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
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return false;
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// Check output modifiers
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if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
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return false;
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return !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp);
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}
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/// \brief This function checks \p MI for operands defined by a move immediate
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/// instruction and then folds the literal constant into the instruction if it
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/// can. This function assumes that \p MI is a VOP1, VOP2, or VOPC instruction
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/// and will only fold literal constants if we are still in SSA.
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static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII,
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MachineRegisterInfo &MRI, bool TryToCommute = true) {
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if (!MRI.isSSA())
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return;
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assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI));
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const SIRegisterInfo &TRI = TII->getRegisterInfo();
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int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);
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MachineOperand &Src0 = MI.getOperand(Src0Idx);
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// Only one literal constant is allowed per instruction, so if src0 is a
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// literal constant then we can't do any folding.
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if (Src0.isImm() &&
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TII->isLiteralConstant(Src0, TII->getOpSize(MI, Src0Idx)))
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return;
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// Literal constants and SGPRs can only be used in Src0, so if Src0 is an
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// SGPR, we cannot commute the instruction, so we can't fold any literal
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// constants.
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if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI))
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return;
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// Try to fold Src0
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if (Src0.isReg() && MRI.hasOneUse(Src0.getReg())) {
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unsigned Reg = Src0.getReg();
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MachineInstr *Def = MRI.getUniqueVRegDef(Reg);
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if (Def && Def->isMoveImmediate()) {
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MachineOperand &MovSrc = Def->getOperand(1);
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bool ConstantFolded = false;
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if (MovSrc.isImm() && isUInt<32>(MovSrc.getImm())) {
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Src0.ChangeToImmediate(MovSrc.getImm());
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ConstantFolded = true;
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}
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if (ConstantFolded) {
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if (MRI.use_empty(Reg))
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Def->eraseFromParent();
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++NumLiteralConstantsFolded;
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return;
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}
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}
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}
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// We have failed to fold src0, so commute the instruction and try again.
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if (TryToCommute && MI.isCommutable() && TII->commuteInstruction(MI))
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foldImmediates(MI, TII, MRI, false);
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}
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// Copy MachineOperand with all flags except setting it as implicit.
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static void copyFlagsToImplicitVCC(MachineInstr &MI,
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const MachineOperand &Orig) {
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for (MachineOperand &Use : MI.implicit_operands()) {
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if (Use.getReg() == AMDGPU::VCC) {
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Use.setIsUndef(Orig.isUndef());
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Use.setIsKill(Orig.isKill());
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return;
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}
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}
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}
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static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) {
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return isInt<16>(Src.getImm()) && !TII->isInlineConstant(Src, 4);
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}
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bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(*MF.getFunction()))
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return false;
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
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const SIInstrInfo *TII = ST.getInstrInfo();
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const SIRegisterInfo &TRI = TII->getRegisterInfo();
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std::vector<unsigned> I1Defs;
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
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BI != BE; ++BI) {
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MachineBasicBlock &MBB = *BI;
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MachineBasicBlock::iterator I, Next;
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for (I = MBB.begin(); I != MBB.end(); I = Next) {
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Next = std::next(I);
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MachineInstr &MI = *I;
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if (MI.getOpcode() == AMDGPU::V_MOV_B32_e32) {
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// If this has a literal constant source that is the same as the
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// reversed bits of an inline immediate, replace with a bitreverse of
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// that constant. This saves 4 bytes in the common case of materializing
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// sign bits.
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// Test if we are after regalloc. We only want to do this after any
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// optimizations happen because this will confuse them.
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// XXX - not exactly a check for post-regalloc run.
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MachineOperand &Src = MI.getOperand(1);
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if (Src.isImm() &&
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TargetRegisterInfo::isPhysicalRegister(MI.getOperand(0).getReg())) {
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int64_t Imm = Src.getImm();
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if (isInt<32>(Imm) && !TII->isInlineConstant(Src, 4)) {
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int32_t ReverseImm = reverseBits<int32_t>(static_cast<int32_t>(Imm));
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if (ReverseImm >= -16 && ReverseImm <= 64) {
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MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32));
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Src.setImm(ReverseImm);
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continue;
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}
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}
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}
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}
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// Combine adjacent s_nops to use the immediate operand encoding how long
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// to wait.
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//
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// s_nop N
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// s_nop M
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// =>
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// s_nop (N + M)
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if (MI.getOpcode() == AMDGPU::S_NOP &&
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Next != MBB.end() &&
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(*Next).getOpcode() == AMDGPU::S_NOP) {
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MachineInstr &NextMI = *Next;
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// The instruction encodes the amount to wait with an offset of 1,
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// i.e. 0 is wait 1 cycle. Convert both to cycles and then convert back
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// after adding.
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uint8_t Nop0 = MI.getOperand(0).getImm() + 1;
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uint8_t Nop1 = NextMI.getOperand(0).getImm() + 1;
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// Make sure we don't overflow the bounds.
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if (Nop0 + Nop1 <= 8) {
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NextMI.getOperand(0).setImm(Nop0 + Nop1 - 1);
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MI.eraseFromParent();
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}
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continue;
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}
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// FIXME: We also need to consider movs of constant operands since
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// immediate operands are not folded if they have more than one use, and
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// the operand folding pass is unaware if the immediate will be free since
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// it won't know if the src == dest constraint will end up being
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// satisfied.
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if (MI.getOpcode() == AMDGPU::S_ADD_I32 ||
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MI.getOpcode() == AMDGPU::S_MUL_I32) {
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const MachineOperand &Dest = MI.getOperand(0);
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const MachineOperand &Src0 = MI.getOperand(1);
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const MachineOperand &Src1 = MI.getOperand(2);
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// FIXME: This could work better if hints worked with subregisters. If
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// we have a vector add of a constant, we usually don't get the correct
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// allocation due to the subregister usage.
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if (TargetRegisterInfo::isVirtualRegister(Dest.getReg()) &&
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Src0.isReg()) {
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MRI.setRegAllocationHint(Dest.getReg(), 0, Src0.getReg());
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continue;
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}
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if (Src0.isReg() && Src0.getReg() == Dest.getReg()) {
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if (Src1.isImm() && isKImmOperand(TII, Src1)) {
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unsigned Opc = (MI.getOpcode() == AMDGPU::S_ADD_I32) ?
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AMDGPU::S_ADDK_I32 : AMDGPU::S_MULK_I32;
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MI.setDesc(TII->get(Opc));
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MI.tieOperands(0, 1);
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}
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}
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}
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// Try to use S_MOVK_I32, which will save 4 bytes for small immediates.
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if (MI.getOpcode() == AMDGPU::S_MOV_B32) {
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const MachineOperand &Src = MI.getOperand(1);
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if (Src.isImm() && isKImmOperand(TII, Src))
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MI.setDesc(TII->get(AMDGPU::S_MOVK_I32));
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continue;
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}
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if (!TII->hasVALU32BitEncoding(MI.getOpcode()))
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continue;
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if (!canShrink(MI, TII, TRI, MRI)) {
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// Try commuting the instruction and see if that enables us to shrink
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// it.
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if (!MI.isCommutable() || !TII->commuteInstruction(MI) ||
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!canShrink(MI, TII, TRI, MRI))
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continue;
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}
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// getVOPe32 could be -1 here if we started with an instruction that had
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// a 32-bit encoding and then commuted it to an instruction that did not.
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if (!TII->hasVALU32BitEncoding(MI.getOpcode()))
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continue;
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int Op32 = AMDGPU::getVOPe32(MI.getOpcode());
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if (TII->isVOPC(Op32)) {
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unsigned DstReg = MI.getOperand(0).getReg();
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if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
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// VOPC instructions can only write to the VCC register. We can't
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// force them to use VCC here, because this is only one register and
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// cannot deal with sequences which would require multiple copies of
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// VCC, e.g. S_AND_B64 (vcc = V_CMP_...), (vcc = V_CMP_...)
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//
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// So, instead of forcing the instruction to write to VCC, we provide
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// a hint to the register allocator to use VCC and then we we will run
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// this pass again after RA and shrink it if it outputs to VCC.
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MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC);
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continue;
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}
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if (DstReg != AMDGPU::VCC)
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continue;
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}
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if (Op32 == AMDGPU::V_CNDMASK_B32_e32) {
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// We shrink V_CNDMASK_B32_e64 using regalloc hints like we do for VOPC
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// instructions.
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const MachineOperand *Src2 =
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TII->getNamedOperand(MI, AMDGPU::OpName::src2);
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if (!Src2->isReg())
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continue;
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unsigned SReg = Src2->getReg();
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if (TargetRegisterInfo::isVirtualRegister(SReg)) {
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MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC);
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continue;
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}
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if (SReg != AMDGPU::VCC)
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continue;
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}
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// We can shrink this instruction
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DEBUG(dbgs() << "Shrinking " << MI);
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MachineInstrBuilder Inst32 =
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BuildMI(MBB, I, MI.getDebugLoc(), TII->get(Op32));
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// Add the dst operand if the 32-bit encoding also has an explicit $vdst.
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// For VOPC instructions, this is replaced by an implicit def of vcc.
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int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst);
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if (Op32DstIdx != -1) {
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// dst
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Inst32.addOperand(MI.getOperand(0));
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} else {
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assert(MI.getOperand(0).getReg() == AMDGPU::VCC &&
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"Unexpected case");
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}
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Inst32.addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::src0));
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const MachineOperand *Src1 =
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TII->getNamedOperand(MI, AMDGPU::OpName::src1);
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if (Src1)
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Inst32.addOperand(*Src1);
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const MachineOperand *Src2 =
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TII->getNamedOperand(MI, AMDGPU::OpName::src2);
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if (Src2) {
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int Op32Src2Idx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2);
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if (Op32Src2Idx != -1) {
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Inst32.addOperand(*Src2);
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} else {
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// In the case of V_CNDMASK_B32_e32, the explicit operand src2 is
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// replaced with an implicit read of vcc. This was already added
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// during the initial BuildMI, so find it to preserve the flags.
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copyFlagsToImplicitVCC(*Inst32, *Src2);
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}
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}
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++NumInstructionsShrunk;
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MI.eraseFromParent();
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foldImmediates(*Inst32, TII, MRI);
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DEBUG(dbgs() << "e32 MI = " << *Inst32 << '\n');
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}
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}
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return false;
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}
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