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941 lines
32 KiB
941 lines
32 KiB
//===--- RDFLiveness.cpp --------------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Computation of the liveness information from the data-flow graph.
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//
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// The main functionality of this code is to compute block live-in
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// information. With the live-in information in place, the placement
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// of kill flags can also be recalculated.
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//
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// The block live-in calculation is based on the ideas from the following
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// publication:
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//
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// Dibyendu Das, Ramakrishna Upadrasta, Benoit Dupont de Dinechin.
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// "Efficient Liveness Computation Using Merge Sets and DJ-Graphs."
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// ACM Transactions on Architecture and Code Optimization, Association for
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// Computing Machinery, 2012, ACM TACO Special Issue on "High-Performance
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// and Embedded Architectures and Compilers", 8 (4),
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// <10.1145/2086696.2086706>. <hal-00647369>
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//
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#include "RDFGraph.h"
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#include "RDFLiveness.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominanceFrontier.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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using namespace rdf;
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namespace llvm {
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namespace rdf {
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template<>
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raw_ostream &operator<< (raw_ostream &OS, const Print<Liveness::RefMap> &P) {
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OS << '{';
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for (auto I : P.Obj) {
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OS << ' ' << Print<RegisterRef>(I.first, P.G) << '{';
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for (auto J = I.second.begin(), E = I.second.end(); J != E; ) {
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OS << Print<NodeId>(*J, P.G);
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if (++J != E)
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OS << ',';
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}
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OS << '}';
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}
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OS << " }";
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return OS;
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}
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} // namespace rdf
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} // namespace llvm
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// The order in the returned sequence is the order of reaching defs in the
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// upward traversal: the first def is the closest to the given reference RefA,
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// the next one is further up, and so on.
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// The list ends at a reaching phi def, or when the reference from RefA is
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// covered by the defs in the list (see FullChain).
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// This function provides two modes of operation:
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// (1) Returning the sequence of reaching defs for a particular reference
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// node. This sequence will terminate at the first phi node [1].
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// (2) Returning a partial sequence of reaching defs, where the final goal
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// is to traverse past phi nodes to the actual defs arising from the code
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// itself.
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// In mode (2), the register reference for which the search was started
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// may be different from the reference node RefA, for which this call was
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// made, hence the argument RefRR, which holds the original register.
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// Also, some definitions may have already been encountered in a previous
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// call that will influence register covering. The register references
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// already defined are passed in through DefRRs.
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// In mode (1), the "continuation" considerations do not apply, and the
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// RefRR is the same as the register in RefA, and the set DefRRs is empty.
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//
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// [1] It is possible for multiple phi nodes to be included in the returned
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// sequence:
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// SubA = phi ...
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// SubB = phi ...
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// ... = SuperAB(rdef:SubA), SuperAB"(rdef:SubB)
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// However, these phi nodes are independent from one another in terms of
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// the data-flow.
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NodeList Liveness::getAllReachingDefs(RegisterRef RefRR,
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NodeAddr<RefNode*> RefA, bool FullChain, const RegisterSet &DefRRs) {
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SetVector<NodeId> DefQ;
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SetVector<NodeId> Owners;
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// The initial queue should not have reaching defs for shadows. The
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// whole point of a shadow is that it will have a reaching def that
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// is not aliased to the reaching defs of the related shadows.
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NodeId Start = RefA.Id;
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auto SNA = DFG.addr<RefNode*>(Start);
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if (NodeId RD = SNA.Addr->getReachingDef())
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DefQ.insert(RD);
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// Collect all the reaching defs, going up until a phi node is encountered,
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// or there are no more reaching defs. From this set, the actual set of
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// reaching defs will be selected.
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// The traversal upwards must go on until a covering def is encountered.
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// It is possible that a collection of non-covering (individually) defs
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// will be sufficient, but keep going until a covering one is found.
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for (unsigned i = 0; i < DefQ.size(); ++i) {
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auto TA = DFG.addr<DefNode*>(DefQ[i]);
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if (TA.Addr->getFlags() & NodeAttrs::PhiRef)
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continue;
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// Stop at the covering/overwriting def of the initial register reference.
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RegisterRef RR = TA.Addr->getRegRef();
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if (RAI.covers(RR, RefRR)) {
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uint16_t Flags = TA.Addr->getFlags();
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if (!(Flags & NodeAttrs::Preserving))
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continue;
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}
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// Get the next level of reaching defs. This will include multiple
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// reaching defs for shadows.
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for (auto S : DFG.getRelatedRefs(TA.Addr->getOwner(DFG), TA))
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if (auto RD = NodeAddr<RefNode*>(S).Addr->getReachingDef())
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DefQ.insert(RD);
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}
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// Remove all non-phi defs that are not aliased to RefRR, and collect
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// the owners of the remaining defs.
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SetVector<NodeId> Defs;
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for (auto N : DefQ) {
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auto TA = DFG.addr<DefNode*>(N);
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bool IsPhi = TA.Addr->getFlags() & NodeAttrs::PhiRef;
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if (!IsPhi && !RAI.alias(RefRR, TA.Addr->getRegRef()))
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continue;
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Defs.insert(TA.Id);
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Owners.insert(TA.Addr->getOwner(DFG).Id);
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}
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// Return the MachineBasicBlock containing a given instruction.
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auto Block = [this] (NodeAddr<InstrNode*> IA) -> MachineBasicBlock* {
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if (IA.Addr->getKind() == NodeAttrs::Stmt)
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return NodeAddr<StmtNode*>(IA).Addr->getCode()->getParent();
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assert(IA.Addr->getKind() == NodeAttrs::Phi);
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NodeAddr<PhiNode*> PA = IA;
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NodeAddr<BlockNode*> BA = PA.Addr->getOwner(DFG);
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return BA.Addr->getCode();
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};
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// Less(A,B) iff instruction A is further down in the dominator tree than B.
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auto Less = [&Block,this] (NodeId A, NodeId B) -> bool {
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if (A == B)
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return false;
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auto OA = DFG.addr<InstrNode*>(A), OB = DFG.addr<InstrNode*>(B);
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MachineBasicBlock *BA = Block(OA), *BB = Block(OB);
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if (BA != BB)
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return MDT.dominates(BB, BA);
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// They are in the same block.
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bool StmtA = OA.Addr->getKind() == NodeAttrs::Stmt;
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bool StmtB = OB.Addr->getKind() == NodeAttrs::Stmt;
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if (StmtA) {
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if (!StmtB) // OB is a phi and phis dominate statements.
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return true;
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auto CA = NodeAddr<StmtNode*>(OA).Addr->getCode();
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auto CB = NodeAddr<StmtNode*>(OB).Addr->getCode();
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// The order must be linear, so tie-break such equalities.
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if (CA == CB)
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return A < B;
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return MDT.dominates(CB, CA);
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} else {
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// OA is a phi.
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if (StmtB)
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return false;
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// Both are phis. There is no ordering between phis (in terms of
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// the data-flow), so tie-break this via node id comparison.
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return A < B;
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}
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};
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std::vector<NodeId> Tmp(Owners.begin(), Owners.end());
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std::sort(Tmp.begin(), Tmp.end(), Less);
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// The vector is a list of instructions, so that defs coming from
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// the same instruction don't need to be artificially ordered.
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// Then, when computing the initial segment, and iterating over an
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// instruction, pick the defs that contribute to the covering (i.e. is
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// not covered by previously added defs). Check the defs individually,
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// i.e. first check each def if is covered or not (without adding them
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// to the tracking set), and then add all the selected ones.
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// The reason for this is this example:
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// *d1<A>, *d2<B>, ... Assume A and B are aliased (can happen in phi nodes).
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// *d3<C> If A \incl BuC, and B \incl AuC, then *d2 would be
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// covered if we added A first, and A would be covered
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// if we added B first.
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NodeList RDefs;
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RegisterSet RRs = DefRRs;
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auto DefInSet = [&Defs] (NodeAddr<RefNode*> TA) -> bool {
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return TA.Addr->getKind() == NodeAttrs::Def &&
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Defs.count(TA.Id);
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};
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for (auto T : Tmp) {
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if (!FullChain && RAI.covers(RRs, RefRR))
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break;
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auto TA = DFG.addr<InstrNode*>(T);
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bool IsPhi = DFG.IsCode<NodeAttrs::Phi>(TA);
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NodeList Ds;
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for (NodeAddr<DefNode*> DA : TA.Addr->members_if(DefInSet, DFG)) {
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auto QR = DA.Addr->getRegRef();
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// Add phi defs even if they are covered by subsequent defs. This is
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// for cases where the reached use is not covered by any of the defs
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// encountered so far: the phi def is needed to expose the liveness
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// of that use to the entry of the block.
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// Example:
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// phi d1<R3>(,d2,), ... Phi def d1 is covered by d2.
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// d2<R3>(d1,,u3), ...
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// ..., u3<D1>(d2) This use needs to be live on entry.
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if (FullChain || IsPhi || !RAI.covers(RRs, QR))
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Ds.push_back(DA);
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}
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RDefs.insert(RDefs.end(), Ds.begin(), Ds.end());
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for (NodeAddr<DefNode*> DA : Ds) {
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// When collecting a full chain of definitions, do not consider phi
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// defs to actually define a register.
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uint16_t Flags = DA.Addr->getFlags();
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if (!FullChain || !(Flags & NodeAttrs::PhiRef))
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if (!(Flags & NodeAttrs::Preserving))
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RRs.insert(DA.Addr->getRegRef());
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}
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}
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return RDefs;
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}
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static const RegisterSet NoRegs;
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NodeList Liveness::getAllReachingDefs(NodeAddr<RefNode*> RefA) {
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return getAllReachingDefs(RefA.Addr->getRegRef(), RefA, false, NoRegs);
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}
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NodeSet Liveness::getAllReachingDefsRec(RegisterRef RefRR,
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NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs) {
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// Collect all defined registers. Do not consider phis to be defining
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// anything, only collect "real" definitions.
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RegisterSet DefRRs;
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for (const auto D : Defs) {
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const auto DA = DFG.addr<const DefNode*>(D);
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if (!(DA.Addr->getFlags() & NodeAttrs::PhiRef))
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DefRRs.insert(DA.Addr->getRegRef());
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}
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auto RDs = getAllReachingDefs(RefRR, RefA, true, DefRRs);
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if (RDs.empty())
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return Defs;
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// Make a copy of the preexisting definitions and add the newly found ones.
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NodeSet TmpDefs = Defs;
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for (auto R : RDs)
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TmpDefs.insert(R.Id);
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NodeSet Result = Defs;
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for (NodeAddr<DefNode*> DA : RDs) {
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Result.insert(DA.Id);
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if (!(DA.Addr->getFlags() & NodeAttrs::PhiRef))
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continue;
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NodeAddr<PhiNode*> PA = DA.Addr->getOwner(DFG);
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if (Visited.count(PA.Id))
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continue;
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Visited.insert(PA.Id);
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// Go over all phi uses and get the reaching defs for each use.
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for (auto U : PA.Addr->members_if(DFG.IsRef<NodeAttrs::Use>, DFG)) {
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const auto &T = getAllReachingDefsRec(RefRR, U, Visited, TmpDefs);
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Result.insert(T.begin(), T.end());
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}
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}
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return Result;
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}
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NodeSet Liveness::getAllReachedUses(RegisterRef RefRR,
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NodeAddr<DefNode*> DefA, const RegisterSet &DefRRs) {
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NodeSet Uses;
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// If the original register is already covered by all the intervening
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// defs, no more uses can be reached.
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if (RAI.covers(DefRRs, RefRR))
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return Uses;
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// Add all directly reached uses.
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NodeId U = DefA.Addr->getReachedUse();
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while (U != 0) {
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auto UA = DFG.addr<UseNode*>(U);
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auto UR = UA.Addr->getRegRef();
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if (RAI.alias(RefRR, UR) && !RAI.covers(DefRRs, UR))
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Uses.insert(U);
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U = UA.Addr->getSibling();
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}
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// Traverse all reached defs.
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for (NodeId D = DefA.Addr->getReachedDef(), NextD; D != 0; D = NextD) {
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auto DA = DFG.addr<DefNode*>(D);
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NextD = DA.Addr->getSibling();
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auto DR = DA.Addr->getRegRef();
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// If this def is already covered, it cannot reach anything new.
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// Similarly, skip it if it is not aliased to the interesting register.
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if (RAI.covers(DefRRs, DR) || !RAI.alias(RefRR, DR))
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continue;
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NodeSet T;
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if (DA.Addr->getFlags() & NodeAttrs::Preserving) {
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// If it is a preserving def, do not update the set of intervening defs.
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T = getAllReachedUses(RefRR, DA, DefRRs);
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} else {
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RegisterSet NewDefRRs = DefRRs;
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NewDefRRs.insert(DR);
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T = getAllReachedUses(RefRR, DA, NewDefRRs);
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}
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Uses.insert(T.begin(), T.end());
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}
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return Uses;
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}
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void Liveness::computePhiInfo() {
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RealUseMap.clear();
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NodeList Phis;
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NodeAddr<FuncNode*> FA = DFG.getFunc();
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auto Blocks = FA.Addr->members(DFG);
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for (NodeAddr<BlockNode*> BA : Blocks) {
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auto Ps = BA.Addr->members_if(DFG.IsCode<NodeAttrs::Phi>, DFG);
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Phis.insert(Phis.end(), Ps.begin(), Ps.end());
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}
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// phi use -> (map: reaching phi -> set of registers defined in between)
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std::map<NodeId,std::map<NodeId,RegisterSet>> PhiUp;
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std::vector<NodeId> PhiUQ; // Work list of phis for upward propagation.
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// Go over all phis.
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for (NodeAddr<PhiNode*> PhiA : Phis) {
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// Go over all defs and collect the reached uses that are non-phi uses
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// (i.e. the "real uses").
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auto &RealUses = RealUseMap[PhiA.Id];
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auto PhiRefs = PhiA.Addr->members(DFG);
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// Have a work queue of defs whose reached uses need to be found.
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// For each def, add to the queue all reached (non-phi) defs.
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SetVector<NodeId> DefQ;
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NodeSet PhiDefs;
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for (auto R : PhiRefs) {
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if (!DFG.IsRef<NodeAttrs::Def>(R))
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continue;
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DefQ.insert(R.Id);
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PhiDefs.insert(R.Id);
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}
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for (unsigned i = 0; i < DefQ.size(); ++i) {
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NodeAddr<DefNode*> DA = DFG.addr<DefNode*>(DefQ[i]);
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NodeId UN = DA.Addr->getReachedUse();
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while (UN != 0) {
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NodeAddr<UseNode*> A = DFG.addr<UseNode*>(UN);
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if (!(A.Addr->getFlags() & NodeAttrs::PhiRef))
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RealUses[getRestrictedRegRef(A)].insert(A.Id);
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UN = A.Addr->getSibling();
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}
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NodeId DN = DA.Addr->getReachedDef();
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while (DN != 0) {
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NodeAddr<DefNode*> A = DFG.addr<DefNode*>(DN);
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for (auto T : DFG.getRelatedRefs(A.Addr->getOwner(DFG), A)) {
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uint16_t Flags = NodeAddr<DefNode*>(T).Addr->getFlags();
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// Must traverse the reached-def chain. Consider:
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// def(D0) -> def(R0) -> def(R0) -> use(D0)
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// The reachable use of D0 passes through a def of R0.
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if (!(Flags & NodeAttrs::PhiRef))
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DefQ.insert(T.Id);
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}
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DN = A.Addr->getSibling();
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}
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}
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// Filter out these uses that appear to be reachable, but really
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// are not. For example:
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//
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// R1:0 = d1
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// = R1:0 u2 Reached by d1.
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// R0 = d3
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// = R1:0 u4 Still reached by d1: indirectly through
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// the def d3.
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// R1 = d5
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// = R1:0 u6 Not reached by d1 (covered collectively
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// by d3 and d5), but following reached
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// defs and uses from d1 will lead here.
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auto HasDef = [&PhiDefs] (NodeAddr<DefNode*> DA) -> bool {
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return PhiDefs.count(DA.Id);
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};
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for (auto UI = RealUses.begin(), UE = RealUses.end(); UI != UE; ) {
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// For each reached register UI->first, there is a set UI->second, of
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// uses of it. For each such use, check if it is reached by this phi,
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// i.e. check if the set of its reaching uses intersects the set of
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// this phi's defs.
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auto &Uses = UI->second;
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for (auto I = Uses.begin(), E = Uses.end(); I != E; ) {
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auto UA = DFG.addr<UseNode*>(*I);
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NodeList RDs = getAllReachingDefs(UI->first, UA);
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if (std::any_of(RDs.begin(), RDs.end(), HasDef))
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++I;
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else
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I = Uses.erase(I);
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}
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if (Uses.empty())
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UI = RealUses.erase(UI);
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else
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++UI;
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}
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// If this phi reaches some "real" uses, add it to the queue for upward
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// propagation.
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if (!RealUses.empty())
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PhiUQ.push_back(PhiA.Id);
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// Go over all phi uses and check if the reaching def is another phi.
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// Collect the phis that are among the reaching defs of these uses.
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// While traversing the list of reaching defs for each phi use, collect
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// the set of registers defined between this phi (Phi) and the owner phi
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// of the reaching def.
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for (auto I : PhiRefs) {
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if (!DFG.IsRef<NodeAttrs::Use>(I))
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continue;
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NodeAddr<UseNode*> UA = I;
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auto &UpMap = PhiUp[UA.Id];
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RegisterSet DefRRs;
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for (NodeAddr<DefNode*> DA : getAllReachingDefs(UA)) {
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if (DA.Addr->getFlags() & NodeAttrs::PhiRef)
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UpMap[DA.Addr->getOwner(DFG).Id] = DefRRs;
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else
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DefRRs.insert(DA.Addr->getRegRef());
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}
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}
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}
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if (Trace) {
|
|
dbgs() << "Phi-up-to-phi map:\n";
|
|
for (auto I : PhiUp) {
|
|
dbgs() << "phi " << Print<NodeId>(I.first, DFG) << " -> {";
|
|
for (auto R : I.second)
|
|
dbgs() << ' ' << Print<NodeId>(R.first, DFG)
|
|
<< Print<RegisterSet>(R.second, DFG);
|
|
dbgs() << " }\n";
|
|
}
|
|
}
|
|
|
|
// Propagate the reached registers up in the phi chain.
|
|
//
|
|
// The following type of situation needs careful handling:
|
|
//
|
|
// phi d1<R1:0> (1)
|
|
// |
|
|
// ... d2<R1>
|
|
// |
|
|
// phi u3<R1:0> (2)
|
|
// |
|
|
// ... u4<R1>
|
|
//
|
|
// The phi node (2) defines a register pair R1:0, and reaches a "real"
|
|
// use u4 of just R1. The same phi node is also known to reach (upwards)
|
|
// the phi node (1). However, the use u4 is not reached by phi (1),
|
|
// because of the intervening definition d2 of R1. The data flow between
|
|
// phis (1) and (2) is restricted to R1:0 minus R1, i.e. R0.
|
|
//
|
|
// When propagating uses up the phi chains, get the all reaching defs
|
|
// for a given phi use, and traverse the list until the propagated ref
|
|
// is covered, or until or until reaching the final phi. Only assume
|
|
// that the reference reaches the phi in the latter case.
|
|
|
|
for (unsigned i = 0; i < PhiUQ.size(); ++i) {
|
|
auto PA = DFG.addr<PhiNode*>(PhiUQ[i]);
|
|
auto &RealUses = RealUseMap[PA.Id];
|
|
for (auto U : PA.Addr->members_if(DFG.IsRef<NodeAttrs::Use>, DFG)) {
|
|
NodeAddr<UseNode*> UA = U;
|
|
auto &UpPhis = PhiUp[UA.Id];
|
|
for (auto UP : UpPhis) {
|
|
bool Changed = false;
|
|
auto &MidDefs = UP.second;
|
|
// Collect the set UpReached of uses that are reached by the current
|
|
// phi PA, and are not covered by any intervening def between PA and
|
|
// the upward phi UP.
|
|
RegisterSet UpReached;
|
|
for (auto T : RealUses) {
|
|
if (!isRestricted(PA, UA, T.first))
|
|
continue;
|
|
if (!RAI.covers(MidDefs, T.first))
|
|
UpReached.insert(T.first);
|
|
}
|
|
if (UpReached.empty())
|
|
continue;
|
|
// Update the set PRUs of real uses reached by the upward phi UP with
|
|
// the actual set of uses (UpReached) that the UP phi reaches.
|
|
auto &PRUs = RealUseMap[UP.first];
|
|
for (auto R : UpReached) {
|
|
unsigned Z = PRUs[R].size();
|
|
PRUs[R].insert(RealUses[R].begin(), RealUses[R].end());
|
|
Changed |= (PRUs[R].size() != Z);
|
|
}
|
|
if (Changed)
|
|
PhiUQ.push_back(UP.first);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (Trace) {
|
|
dbgs() << "Real use map:\n";
|
|
for (auto I : RealUseMap) {
|
|
dbgs() << "phi " << Print<NodeId>(I.first, DFG);
|
|
NodeAddr<PhiNode*> PA = DFG.addr<PhiNode*>(I.first);
|
|
NodeList Ds = PA.Addr->members_if(DFG.IsRef<NodeAttrs::Def>, DFG);
|
|
if (!Ds.empty()) {
|
|
RegisterRef RR = NodeAddr<DefNode*>(Ds[0]).Addr->getRegRef();
|
|
dbgs() << '<' << Print<RegisterRef>(RR, DFG) << '>';
|
|
} else {
|
|
dbgs() << "<noreg>";
|
|
}
|
|
dbgs() << " -> " << Print<RefMap>(I.second, DFG) << '\n';
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void Liveness::computeLiveIns() {
|
|
// Populate the node-to-block map. This speeds up the calculations
|
|
// significantly.
|
|
NBMap.clear();
|
|
for (NodeAddr<BlockNode*> BA : DFG.getFunc().Addr->members(DFG)) {
|
|
MachineBasicBlock *BB = BA.Addr->getCode();
|
|
for (NodeAddr<InstrNode*> IA : BA.Addr->members(DFG)) {
|
|
for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG))
|
|
NBMap.insert(std::make_pair(RA.Id, BB));
|
|
NBMap.insert(std::make_pair(IA.Id, BB));
|
|
}
|
|
}
|
|
|
|
MachineFunction &MF = DFG.getMF();
|
|
|
|
// Compute IDF first, then the inverse.
|
|
decltype(IIDF) IDF;
|
|
for (auto &B : MF) {
|
|
auto F1 = MDF.find(&B);
|
|
if (F1 == MDF.end())
|
|
continue;
|
|
SetVector<MachineBasicBlock*> IDFB(F1->second.begin(), F1->second.end());
|
|
for (unsigned i = 0; i < IDFB.size(); ++i) {
|
|
auto F2 = MDF.find(IDFB[i]);
|
|
if (F2 != MDF.end())
|
|
IDFB.insert(F2->second.begin(), F2->second.end());
|
|
}
|
|
// Add B to the IDF(B). This will put B in the IIDF(B).
|
|
IDFB.insert(&B);
|
|
IDF[&B].insert(IDFB.begin(), IDFB.end());
|
|
}
|
|
|
|
for (auto I : IDF)
|
|
for (auto S : I.second)
|
|
IIDF[S].insert(I.first);
|
|
|
|
computePhiInfo();
|
|
|
|
NodeAddr<FuncNode*> FA = DFG.getFunc();
|
|
auto Blocks = FA.Addr->members(DFG);
|
|
|
|
// Build the phi live-on-entry map.
|
|
for (NodeAddr<BlockNode*> BA : Blocks) {
|
|
MachineBasicBlock *MB = BA.Addr->getCode();
|
|
auto &LON = PhiLON[MB];
|
|
for (auto P : BA.Addr->members_if(DFG.IsCode<NodeAttrs::Phi>, DFG))
|
|
for (auto S : RealUseMap[P.Id])
|
|
LON[S.first].insert(S.second.begin(), S.second.end());
|
|
}
|
|
|
|
if (Trace) {
|
|
dbgs() << "Phi live-on-entry map:\n";
|
|
for (auto I : PhiLON)
|
|
dbgs() << "block #" << I.first->getNumber() << " -> "
|
|
<< Print<RefMap>(I.second, DFG) << '\n';
|
|
}
|
|
|
|
// Build the phi live-on-exit map. Each phi node has some set of reached
|
|
// "real" uses. Propagate this set backwards into the block predecessors
|
|
// through the reaching defs of the corresponding phi uses.
|
|
for (NodeAddr<BlockNode*> BA : Blocks) {
|
|
auto Phis = BA.Addr->members_if(DFG.IsCode<NodeAttrs::Phi>, DFG);
|
|
for (NodeAddr<PhiNode*> PA : Phis) {
|
|
auto &RUs = RealUseMap[PA.Id];
|
|
if (RUs.empty())
|
|
continue;
|
|
|
|
for (auto U : PA.Addr->members_if(DFG.IsRef<NodeAttrs::Use>, DFG)) {
|
|
NodeAddr<PhiUseNode*> UA = U;
|
|
if (UA.Addr->getReachingDef() == 0)
|
|
continue;
|
|
|
|
// Mark all reached "real" uses of P as live on exit in the
|
|
// predecessor.
|
|
// Remap all the RUs so that they have a correct reaching def.
|
|
auto PrA = DFG.addr<BlockNode*>(UA.Addr->getPredecessor());
|
|
auto &LOX = PhiLOX[PrA.Addr->getCode()];
|
|
for (auto R : RUs) {
|
|
RegisterRef RR = R.first;
|
|
if (!isRestricted(PA, UA, RR))
|
|
RR = getRestrictedRegRef(UA);
|
|
// The restricted ref may be different from the ref that was
|
|
// accessed in the "real use". This means that this phi use
|
|
// is not the one that carries this reference, so skip it.
|
|
if (!RAI.alias(R.first, RR))
|
|
continue;
|
|
for (auto D : getAllReachingDefs(RR, UA))
|
|
LOX[RR].insert(D.Id);
|
|
}
|
|
} // for U : phi uses
|
|
} // for P : Phis
|
|
} // for B : Blocks
|
|
|
|
if (Trace) {
|
|
dbgs() << "Phi live-on-exit map:\n";
|
|
for (auto I : PhiLOX)
|
|
dbgs() << "block #" << I.first->getNumber() << " -> "
|
|
<< Print<RefMap>(I.second, DFG) << '\n';
|
|
}
|
|
|
|
RefMap LiveIn;
|
|
traverse(&MF.front(), LiveIn);
|
|
|
|
// Add function live-ins to the live-in set of the function entry block.
|
|
auto &EntryIn = LiveMap[&MF.front()];
|
|
for (auto I = MRI.livein_begin(), E = MRI.livein_end(); I != E; ++I)
|
|
EntryIn.insert({I->first,0});
|
|
|
|
if (Trace) {
|
|
// Dump the liveness map
|
|
for (auto &B : MF) {
|
|
BitVector LV(TRI.getNumRegs());
|
|
for (auto I = B.livein_begin(), E = B.livein_end(); I != E; ++I)
|
|
LV.set(I->PhysReg);
|
|
dbgs() << "BB#" << B.getNumber() << "\t rec = {";
|
|
for (int x = LV.find_first(); x >= 0; x = LV.find_next(x))
|
|
dbgs() << ' ' << Print<RegisterRef>({unsigned(x),0}, DFG);
|
|
dbgs() << " }\n";
|
|
dbgs() << "\tcomp = " << Print<RegisterSet>(LiveMap[&B], DFG) << '\n';
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void Liveness::resetLiveIns() {
|
|
for (auto &B : DFG.getMF()) {
|
|
// Remove all live-ins.
|
|
std::vector<unsigned> T;
|
|
for (auto I = B.livein_begin(), E = B.livein_end(); I != E; ++I)
|
|
T.push_back(I->PhysReg);
|
|
for (auto I : T)
|
|
B.removeLiveIn(I);
|
|
// Add the newly computed live-ins.
|
|
auto &LiveIns = LiveMap[&B];
|
|
for (auto I : LiveIns) {
|
|
assert(I.Sub == 0);
|
|
B.addLiveIn(I.Reg);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void Liveness::resetKills() {
|
|
for (auto &B : DFG.getMF())
|
|
resetKills(&B);
|
|
}
|
|
|
|
|
|
void Liveness::resetKills(MachineBasicBlock *B) {
|
|
auto CopyLiveIns = [] (MachineBasicBlock *B, BitVector &LV) -> void {
|
|
for (auto I = B->livein_begin(), E = B->livein_end(); I != E; ++I)
|
|
LV.set(I->PhysReg);
|
|
};
|
|
|
|
BitVector LiveIn(TRI.getNumRegs()), Live(TRI.getNumRegs());
|
|
CopyLiveIns(B, LiveIn);
|
|
for (auto SI : B->successors())
|
|
CopyLiveIns(SI, Live);
|
|
|
|
for (auto I = B->rbegin(), E = B->rend(); I != E; ++I) {
|
|
MachineInstr *MI = &*I;
|
|
if (MI->isDebugValue())
|
|
continue;
|
|
|
|
MI->clearKillInfo();
|
|
for (auto &Op : MI->operands()) {
|
|
// An implicit def of a super-register may not necessarily start a
|
|
// live range of it, since an implicit use could be used to keep parts
|
|
// of it live. Instead of analyzing the implicit operands, ignore
|
|
// implicit defs.
|
|
if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
|
|
continue;
|
|
unsigned R = Op.getReg();
|
|
if (!TargetRegisterInfo::isPhysicalRegister(R))
|
|
continue;
|
|
for (MCSubRegIterator SR(R, &TRI, true); SR.isValid(); ++SR)
|
|
Live.reset(*SR);
|
|
}
|
|
for (auto &Op : MI->operands()) {
|
|
if (!Op.isReg() || !Op.isUse())
|
|
continue;
|
|
unsigned R = Op.getReg();
|
|
if (!TargetRegisterInfo::isPhysicalRegister(R))
|
|
continue;
|
|
bool IsLive = false;
|
|
for (MCRegAliasIterator AR(R, &TRI, true); AR.isValid(); ++AR) {
|
|
if (!Live[*AR])
|
|
continue;
|
|
IsLive = true;
|
|
break;
|
|
}
|
|
if (IsLive)
|
|
continue;
|
|
Op.setIsKill(true);
|
|
for (MCSubRegIterator SR(R, &TRI, true); SR.isValid(); ++SR)
|
|
Live.set(*SR);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
// For shadows, determine if RR is aliased to a reaching def of any other
|
|
// shadow associated with RA. If it is not, then RR is "restricted" to RA,
|
|
// and so it can be considered a value specific to RA. This is important
|
|
// for accurately determining values associated with phi uses.
|
|
// For non-shadows, this function returns "true".
|
|
bool Liveness::isRestricted(NodeAddr<InstrNode*> IA, NodeAddr<RefNode*> RA,
|
|
RegisterRef RR) const {
|
|
NodeId Start = RA.Id;
|
|
for (NodeAddr<RefNode*> TA = DFG.getNextShadow(IA, RA);
|
|
TA.Id != 0 && TA.Id != Start; TA = DFG.getNextShadow(IA, TA)) {
|
|
NodeId RD = TA.Addr->getReachingDef();
|
|
if (RD == 0)
|
|
continue;
|
|
if (RAI.alias(RR, DFG.addr<DefNode*>(RD).Addr->getRegRef()))
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
|
|
RegisterRef Liveness::getRestrictedRegRef(NodeAddr<RefNode*> RA) const {
|
|
assert(DFG.IsRef<NodeAttrs::Use>(RA));
|
|
if (RA.Addr->getFlags() & NodeAttrs::Shadow) {
|
|
NodeId RD = RA.Addr->getReachingDef();
|
|
assert(RD);
|
|
RA = DFG.addr<DefNode*>(RD);
|
|
}
|
|
return RA.Addr->getRegRef();
|
|
}
|
|
|
|
|
|
unsigned Liveness::getPhysReg(RegisterRef RR) const {
|
|
if (!TargetRegisterInfo::isPhysicalRegister(RR.Reg))
|
|
return 0;
|
|
return RR.Sub ? TRI.getSubReg(RR.Reg, RR.Sub) : RR.Reg;
|
|
}
|
|
|
|
|
|
// Helper function to obtain the basic block containing the reaching def
|
|
// of the given use.
|
|
MachineBasicBlock *Liveness::getBlockWithRef(NodeId RN) const {
|
|
auto F = NBMap.find(RN);
|
|
if (F != NBMap.end())
|
|
return F->second;
|
|
llvm_unreachable("Node id not in map");
|
|
}
|
|
|
|
|
|
void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) {
|
|
// The LiveIn map, for each (physical) register, contains the set of live
|
|
// reaching defs of that register that are live on entry to the associated
|
|
// block.
|
|
|
|
// The summary of the traversal algorithm:
|
|
//
|
|
// R is live-in in B, if there exists a U(R), such that rdef(R) dom B
|
|
// and (U \in IDF(B) or B dom U).
|
|
//
|
|
// for (C : children) {
|
|
// LU = {}
|
|
// traverse(C, LU)
|
|
// LiveUses += LU
|
|
// }
|
|
//
|
|
// LiveUses -= Defs(B);
|
|
// LiveUses += UpwardExposedUses(B);
|
|
// for (C : IIDF[B])
|
|
// for (U : LiveUses)
|
|
// if (Rdef(U) dom C)
|
|
// C.addLiveIn(U)
|
|
//
|
|
|
|
// Go up the dominator tree (depth-first).
|
|
MachineDomTreeNode *N = MDT.getNode(B);
|
|
for (auto I : *N) {
|
|
RefMap L;
|
|
MachineBasicBlock *SB = I->getBlock();
|
|
traverse(SB, L);
|
|
|
|
for (auto S : L)
|
|
LiveIn[S.first].insert(S.second.begin(), S.second.end());
|
|
}
|
|
|
|
if (Trace) {
|
|
dbgs() << LLVM_FUNCTION_NAME << " in BB#" << B->getNumber()
|
|
<< " after recursion into";
|
|
for (auto I : *N)
|
|
dbgs() << ' ' << I->getBlock()->getNumber();
|
|
dbgs() << "\n LiveIn: " << Print<RefMap>(LiveIn, DFG);
|
|
dbgs() << "\n Local: " << Print<RegisterSet>(LiveMap[B], DFG) << '\n';
|
|
}
|
|
|
|
// Add phi uses that are live on exit from this block.
|
|
RefMap &PUs = PhiLOX[B];
|
|
for (auto S : PUs)
|
|
LiveIn[S.first].insert(S.second.begin(), S.second.end());
|
|
|
|
if (Trace) {
|
|
dbgs() << "after LOX\n";
|
|
dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
|
|
dbgs() << " Local: " << Print<RegisterSet>(LiveMap[B], DFG) << '\n';
|
|
}
|
|
|
|
// Stop tracking all uses defined in this block: erase those records
|
|
// where the reaching def is located in B and which cover all reached
|
|
// uses.
|
|
auto Copy = LiveIn;
|
|
LiveIn.clear();
|
|
|
|
for (auto I : Copy) {
|
|
auto &Defs = LiveIn[I.first];
|
|
NodeSet Rest;
|
|
for (auto R : I.second) {
|
|
auto DA = DFG.addr<DefNode*>(R);
|
|
RegisterRef DDR = DA.Addr->getRegRef();
|
|
NodeAddr<InstrNode*> IA = DA.Addr->getOwner(DFG);
|
|
NodeAddr<BlockNode*> BA = IA.Addr->getOwner(DFG);
|
|
// Defs from a different block need to be preserved. Defs from this
|
|
// block will need to be processed further, except for phi defs, the
|
|
// liveness of which is handled through the PhiLON/PhiLOX maps.
|
|
if (B != BA.Addr->getCode())
|
|
Defs.insert(R);
|
|
else {
|
|
bool IsPreserving = DA.Addr->getFlags() & NodeAttrs::Preserving;
|
|
if (IA.Addr->getKind() != NodeAttrs::Phi && !IsPreserving) {
|
|
bool Covering = RAI.covers(DDR, I.first);
|
|
NodeId U = DA.Addr->getReachedUse();
|
|
while (U && Covering) {
|
|
auto DUA = DFG.addr<UseNode*>(U);
|
|
RegisterRef Q = DUA.Addr->getRegRef();
|
|
Covering = RAI.covers(DA.Addr->getRegRef(), Q);
|
|
U = DUA.Addr->getSibling();
|
|
}
|
|
if (!Covering)
|
|
Rest.insert(R);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Non-covering defs from B.
|
|
for (auto R : Rest) {
|
|
auto DA = DFG.addr<DefNode*>(R);
|
|
RegisterRef DRR = DA.Addr->getRegRef();
|
|
RegisterSet RRs;
|
|
for (NodeAddr<DefNode*> TA : getAllReachingDefs(DA)) {
|
|
NodeAddr<InstrNode*> IA = TA.Addr->getOwner(DFG);
|
|
NodeAddr<BlockNode*> BA = IA.Addr->getOwner(DFG);
|
|
// Preserving defs do not count towards covering.
|
|
if (!(TA.Addr->getFlags() & NodeAttrs::Preserving))
|
|
RRs.insert(TA.Addr->getRegRef());
|
|
if (BA.Addr->getCode() == B)
|
|
continue;
|
|
if (RAI.covers(RRs, DRR))
|
|
break;
|
|
Defs.insert(TA.Id);
|
|
}
|
|
}
|
|
}
|
|
|
|
emptify(LiveIn);
|
|
|
|
if (Trace) {
|
|
dbgs() << "after defs in block\n";
|
|
dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
|
|
dbgs() << " Local: " << Print<RegisterSet>(LiveMap[B], DFG) << '\n';
|
|
}
|
|
|
|
// Scan the block for upward-exposed uses and add them to the tracking set.
|
|
for (auto I : DFG.getFunc().Addr->findBlock(B, DFG).Addr->members(DFG)) {
|
|
NodeAddr<InstrNode*> IA = I;
|
|
if (IA.Addr->getKind() != NodeAttrs::Stmt)
|
|
continue;
|
|
for (NodeAddr<UseNode*> UA : IA.Addr->members_if(DFG.IsUse, DFG)) {
|
|
RegisterRef RR = UA.Addr->getRegRef();
|
|
for (auto D : getAllReachingDefs(UA))
|
|
if (getBlockWithRef(D.Id) != B)
|
|
LiveIn[RR].insert(D.Id);
|
|
}
|
|
}
|
|
|
|
if (Trace) {
|
|
dbgs() << "after uses in block\n";
|
|
dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
|
|
dbgs() << " Local: " << Print<RegisterSet>(LiveMap[B], DFG) << '\n';
|
|
}
|
|
|
|
// Phi uses should not be propagated up the dominator tree, since they
|
|
// are not dominated by their corresponding reaching defs.
|
|
auto &Local = LiveMap[B];
|
|
auto &LON = PhiLON[B];
|
|
for (auto R : LON)
|
|
Local.insert(R.first);
|
|
|
|
if (Trace) {
|
|
dbgs() << "after phi uses in block\n";
|
|
dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
|
|
dbgs() << " Local: " << Print<RegisterSet>(Local, DFG) << '\n';
|
|
}
|
|
|
|
for (auto C : IIDF[B]) {
|
|
auto &LiveC = LiveMap[C];
|
|
for (auto S : LiveIn)
|
|
for (auto R : S.second)
|
|
if (MDT.properlyDominates(getBlockWithRef(R), C))
|
|
LiveC.insert(S.first);
|
|
}
|
|
}
|
|
|
|
|
|
void Liveness::emptify(RefMap &M) {
|
|
for (auto I = M.begin(), E = M.end(); I != E; )
|
|
I = I->second.empty() ? M.erase(I) : std::next(I);
|
|
}
|
|
|