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45 lines
1.8 KiB
45 lines
1.8 KiB
/* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef __CROS_EC_FLASH_LAYOUT_H
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#define __CROS_EC_FLASH_LAYOUT_H
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/*
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* The flash memory is implemented in two halves. The SoC bootrom will look for
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* a first-stage bootloader (aka "RO firmware") at the beginning of each of the
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* two halves and prefer the newer one if both are valid. The chosen bootloader
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* also looks in each half of the flash for a valid application image ("RW
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* firmware"), so we have two possible RW images as well. The RO and RW images
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* are not tightly coupled, so either RO image can choose to boot either RW
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* image. RO images are provided by the SoC team, and can be updated separately
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* from the RW images.
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*/
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#define CITADEL_FLASH_BASE 0x40000
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#define CITADEL_FLASH_SIZE (512 * 1024)
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#define CITADEL_FLASH_HALF (CITADEL_FLASH_SIZE >> 1)
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#define CITADEL_RO_SIZE 0x4000
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#define CITADEL_RO_A_MEM_OFF 0
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#define CITADEL_RO_B_MEM_OFF CITADEL_FLASH_HALF
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#define CITADEL_RW_A_MEM_OFF CITADEL_RO_SIZE
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#define CITADEL_RW_B_MEM_OFF (CITADEL_FLASH_HALF + CITADEL_RW_A_MEM_OFF)
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#define DAUNTLESS_FLASH_BASE 0x80000
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#define DAUNTLESS_FLASH_SIZE (1024 * 1024)
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#define DAUNTLESS_FLASH_HALF (DAUNTLESS_FLASH_SIZE >> 1)
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#define DAUNTLESS_RO_SIZE 0x4000
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#define DAUNTLESS_RO_A_MEM_OFF 0
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#define DAUNTLESS_RO_B_MEM_OFF DAUNTLESS_FLASH_HALF
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#define DAUNTLESS_RW_A_MEM_OFF DAUNTLESS_RO_SIZE
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#define DAUNTLESS_RW_B_MEM_OFF (DAUNTLESS_FLASH_HALF + DAUNTLESS_RW_A_MEM_OFF)
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/*
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* Citadel reserves 0x4000 bytes (16K) for its RO firmware. Dauntless can vary,
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* but the RW firmware will follow RO and be aligned on a 16K boundary.
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*/
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#define FLASH_RW_ALIGNMENT 0x4000
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#endif /* __CROS_EC_FLASH_LAYOUT_H */
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