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262 lines
9.8 KiB
262 lines
9.8 KiB
/*
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* Copyright (c) Hisilicon Technologies Co., Ltd.. 2019-2019. All rights reserved.
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* Description: hdmi driver main header file
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* Author: Hisilicon
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* Create: 2019-06-22
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*/
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#ifndef __DRV_HDMITX_H__
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#define __DRV_HDMITX_H__
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#include <td_type.h>
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#include "osal_ext.h"
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#include "drv_hdmitx_ext.h"
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#include "drv_repeater_dip.h"
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#include "drv_ao_dip.h"
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#include "drv_hdmitx_common.h"
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#include "drv_hdmitx_infoframe.h"
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/* switch mode define */
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#define HDMITX_SWITCH_MODE_TMDS_2_TMDS 0
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#define HDMITX_SWITCH_MODE_TMDS_2_FRL 1
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#define HDMITX_SWITCH_MODE_FRL_2_TMDS 2
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#define HDMITX_SWITCH_MODE_FRL_2_FRL 3
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struct ext_hdmitx;
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struct avi_infoframe {
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td_bool enable;
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struct hdmitx_avi_infoframe avi;
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};
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struct hf14_vsif_infoframe {
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td_bool enable;
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struct hdmitx_vendor_infoframe hf14;
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};
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struct dolby_vsif_infoframe {
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td_bool enable;
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struct hdmitx_dolby_vendor_infoframe dolby;
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};
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struct cuva_monitor_vsif_infoframe {
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td_bool enable;
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struct hdmitx_cuva_monitor_vsif cuva_monitor;
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};
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struct hf_vsif_infoframe {
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td_bool enable;
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struct hdmitx_forum_vendor_infoframe hf_vsif;
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};
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struct drm_infoframe {
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td_u32 drm_type;
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struct hdmitx_drm_infoframe drm;
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};
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struct vrr_infoframe {
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td_bool enable;
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struct hdmitx_vt_ext_metadata vrr;
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};
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struct cuva_hdr_infoframe {
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td_bool enable;
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struct hdmitx_cuva_hdr_ext_metadata cuva;
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};
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struct hdmitx_infoframe {
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/* avi infoframe */
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struct avi_infoframe avi_info;
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/* vendor infoframe */
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struct hf14_vsif_infoframe hf14_vsif; /* for hdmi1.4 or dolby vision v2 */
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struct hf_vsif_infoframe hf_vsif; /* for allm */
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struct dolby_vsif_infoframe dolby_vsif; /* for dolby vision v3 */
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struct drm_infoframe drm_info;
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struct vrr_infoframe vrr_info;
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struct cuva_hdr_infoframe cuva_hdr_info;
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struct cuva_monitor_vsif_infoframe cuva_monitor_info;
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};
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/*
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* @attach: This callback function is used when bind a vo to a display interface
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* @dettach: This callback function is used when unbind a vo with a display interface
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* @mode_validate: This called is used to validate the if the mode is supported by the interface or not
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* before setting the display mode.
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* @prepare: This callback should prepare the display interface for a subsequent modeset
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* @mode_set: This callback is used to update the display mode of an display interface.
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* @display_on: This callback is used to turn on the interface signal to the display
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* @display_off: This callback is used to turn off the interface signal to the display
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*/
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struct hdmitx_vo_ops {
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td_void (*suspend)(struct ext_hdmitx *dev, td_bool lower_power);
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td_s32 (*resume)(struct ext_hdmitx *dev, td_bool lower_power);
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td_s32 (*attach)(const struct ext_hdmitx *dev, const td_void *data);
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td_s32 (*detach)(const struct ext_hdmitx *dev, const td_void *data);
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td_s32 (*mode_validate)(const struct ext_hdmitx *dev, td_u32 mode, struct ext_display_mode *dispaly_mode);
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td_s32 (*prepare)(struct ext_hdmitx *dev, td_u32 mode, struct ext_display_mode *dispaly_mode);
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td_s32 (*mode_set)(struct ext_hdmitx *dev, td_u32 mode);
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td_s32 (*atomic_mode_set)(const struct ext_hdmitx *dev, td_u32 mode,
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const struct ext_display_mode *dispaly_mode);
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td_s32 (*display_on)(const struct ext_hdmitx *dev);
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td_s32 (*display_off)(struct ext_hdmitx *dev);
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};
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struct hdmitx_ao_ops {
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/* get sink's audio capability */
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td_s32 (*get_eld)(const struct ext_hdmitx *dev, const td_void *data, td_u8 *buf, td_size_t len);
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/* check audio attr valid */
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td_s32 (*hw_params_validate)(const struct ext_hdmitx *dev, const struct ao_attr *attr);
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/* set audio attr */
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td_s32 (*hw_params)(const struct ext_hdmitx *dev, const struct ao_attr *attr);
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/* mute hdmi audio */
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td_s32 (*digital_mute)(const struct ext_hdmitx *dev, const td_void *data, td_bool enable);
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/* detect hdmi hotplug status */
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td_s32 (*hpd_detect)(const struct ext_hdmitx *dev, td_u32 *status);
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/* used to received audio interface broadcast msg */
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td_s32 (*register_notifier)(struct ext_hdmitx *dev, struct hdmitx_notifier *notifier);
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td_s32 (*unregister_notifier)(struct ext_hdmitx *dev, const struct hdmitx_notifier *notifier);
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};
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struct ext_hdmitx {
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td_u32 id;
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td_u32 version;
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osal_dev hdmitx_dev; /* This is for IOCTL */
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td_bool attached; /* whether the hdmi is attached */
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td_s8 name[16]; /* name max size is 16. */
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struct hdmitx_phy *phy; /* Phy reference */
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struct hdmitx_controller *controller;
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struct hdmitx_crg *crg;
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struct hdmitx_notifier_head notifier_list; /* Notifier head, now only for ao */
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osal_mutex notifier_mutex;
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osal_mutex disp_mutex;
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struct hdmitx_vo_ops *vo_ops;
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struct hdmitx_ao_ops *ao_ops;
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td_bool is_suspend;
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td_bool is_start_output;
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osal_delayedwork work_compat_hdr;
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struct hdmitx_infoframe per_infoframe;
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struct hdmitx_infoframe cur_infoframe;
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osal_semaphore ioctl_mutex;
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};
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/*
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* hdmi source capability -caps
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* bit0: cec_support 0: no support; 1: support.
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* bit1: hdcp14_support 0: no support; 1: support.
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* bit2: hdcp2x_support 0: no support; 1: support.
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* bit3: dvi_support 0: no support; 1: support.
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* bit4: hdmi_support 0: no support; 1: support.
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* bit5: max_tmds_clock 0: 340M; 1: 600M.
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* bit6: scdc_present 0: no support; 1: support.
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* bit7: scdc_lte_340mcsc 0: no support; 1: support.
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* bit8: bpc_30 0: no support; 1: support.
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* bit9: bpc_36 0: no support; 1: support.
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* bit10: bpc_48 0: no support; 1: support.
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* bit11-14: max_frl_rate 0: no support; 1: 3G3L; 2: 6G3L; 3: 6G4L;
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* 4: 8G4L; 5: 10G4L; 6: 12G4L; [7~15]: RESVER.
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* bit15-17: ffe_levels 0: FFE0; 1: FFE1; 2: FFE2; 3: FFE3; [4~7]: RESVER.
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* bit18: dsc_support 0: no support; 1: support;
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* bit19: native_y420 0: no support; 1: support;
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* bit20: dsc_10bpc 0: no support; 1: support;
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* bit21: dsc_12bpc 0: no support; 1: support;
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* bit22-25: max_slice_count 0: no support; 1: 1 slices; 2: 2 slices;
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* 3: 4 slices; 4: 8 slices; 5: 12 slices;
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* 6: 16 slices; [7~15]: RESVER.
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* bit26-27: max_pixel_clk_per_slice 0: 340; 1: 400; [2~3]: RESVER.
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* bit28: rgb2yuv 0: no support; 1: support.
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* bit29: ycbcr444 0: no support; 1: support.
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* bit30: ycbcr422 0: no support; 1: support.
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* bit31: ycbcr420 0: no support; 1: support.
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*/
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/* bit0: cec */
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#define CEC_SUPPORT_MASK (1 << 0)
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#define CEC_SUPPORT_SHIFT 0
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/* bit1~2:hdcp */
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#define HDCP14_SUPPORT_MASK (1 << 1)
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#define HDCP14_SUPPORT_SHIFT 1
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#define HDCP2X_SUPPORT_MASK (1 << 2)
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#define HDCP2X_SUPPORT_SHIFT 2
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/* bit3~5:tmds */
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#define DVI_SUPPORT_MASK (1 << 3)
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#define DVI_SUPPORT_SHIFT 3
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#define HDMITX_SUPPORT_MASK (1 << 4)
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#define HDMI_SUPPORT_SHIFT 4
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#define MAX_TMDS_CLOCK_MASK (1 << 5)
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#define MAX_TMDS_CLOCK_SHIFT 5
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/* bit6~7:scdc */
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#define SCDC_PRESENT_MASK (1 << 6)
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#define SCDC_PRESENT_SHIFT 6
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#define SCDC_LTE_340MCSC_MASK (1 << 7)
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#define SCDC_LTE_340MCSC_SHIFT 7
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/* bit8~10:deepcolor */
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#define BPC_30_MASK (1 << 8)
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#define BPC_30_SHIFT 8
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#define BPC_36_MASK (1 << 9)
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#define BPC_36_SHIFT 9
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#define BPC_48_MASK (1 << 10)
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#define BPC_48_SHIFT 10
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/* bit11~17:frl */
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#define MAX_FRL_RATE_MASK (0xf << 11)
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#define MAX_FRL_RATE_SHIFT 11
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#define FFE_LEVELS_MASK (0x7 << 15)
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#define FFE_LEVELS_SHIFT 15
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/* bit18~27:dsc */
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#define DSC_SUPPORT_MASK (1 << 18)
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#define DSC_SUPPORT_SHIFT 18
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#define NATIVE_Y420_MASK (1 << 19)
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#define NATIVE_Y420_SHIFT 19
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#define DSC_10BPC_MASK (1 << 20)
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#define DSC_10BPC_SHIFT 20
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#define DSC_12BPC_MASK (1 << 21)
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#define DSC_12BPC_SHIFT 21
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#define MAX_SLICE_COUNT_MASK (0xf << 22)
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#define MAX_SLICE_COUNT_SHIFT 22
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#define MAX_PIXEL_CLK_PER_SLICE_MASK (0x3 << 26)
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#define MAX_PIXEL_CLK_PER_SLICE_SHIFT 26
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/* bit28~31:csc */
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#define RGB2YUV_MASK (1 << 28)
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#define RGB2YUV_SHIFT 28
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#define YCBCR444_MASK (1 << 29)
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#define YCBCR444_SHIFT 29
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#define YCBCR422_MASK (1 << 30)
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#define YCBCR422_SHIFT 30
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#define YCBCR420_MASK (1 << 31)
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#define YCBCR420_SHIFT 31
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/*
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* hdmi source capability 2 -caps2
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* bit0: yuv2rgb 0: no support; 1: support.
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* bit1: dither_support 0: no support; 1: support.
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* bit2-5: max_pixel_clock 0: 340M; 1: 600M; 2: 1188M; 3: 2376M;
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* 4: 4752M; [5~15]: RESVER.
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* bit6: vrr_support 0: no support; 1: support.
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* bit7: cuva_support 0: no support; 1: support.
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* bit8-31: reserved.
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*/
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/* bit0~1: csc */
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#define YUV2RGB_MASK (1 << 0)
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#define YUV2RGB_SHIFT 0
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#define DITHER_SUPPORT_MASK (1 << 1)
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#define DITHER_SUPPORT_SHIFT 1
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/* bit2-5: max_pixel_clock */
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#define MAX_PIXEL_CLOCK_MASK (0xf << 2)
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#define MAX_PIXEL_CLOCK_SHIFT 2
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/* bit6: vrr_support */
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#define VRR_MASK (1 << 6)
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#define VRR_SHIFT 6
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/* bit7: cuva_support */
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#define CUVA_MASK (1 << 7)
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#define CUVA_SHIFT 7
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#define HDMITX_PROTOCAL_VERSION_1_4 0x1
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#define HDMITX_PROTOCAL_VERSION_2_0 0x2
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#define HDMITX_PROTOCAL_VERSION_2_1 0x3
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td_void hdmi_sysfs_event(osal_dev *hdmitx_dev, td_char *event, td_u32 size);
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td_s32 hdmi_phy_fcg_set(const struct ext_hdmitx *hdmi);
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td_void hdmi_crg_set(const struct ext_hdmitx *hdmi);
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td_void hdmi_ao_notifiers(struct ext_hdmitx *hdmi, td_u32 val);
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td_void drv_hdmitx_disp_event(struct ext_hdmitx *hdmi, ext_drv_rpt_tx_event event);
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td_s32 hdmitx_set_phy_cross_en(td_bool enable);
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#endif
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