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192 lines
6.5 KiB
192 lines
6.5 KiB
/*
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* Copyright (c) Hisilicon Technologies Co., Ltd. 2021-2021. All rights reserved.
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* Description: Entries for drviers and applications
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* Author: Hisilicon
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* Create: 2021-04-26
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*/
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#include "soc_osal.h"
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#include "td_type.h"
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#include "arch/pmp.h"
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#include "board.h"
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#include "drv_dmcu_sys.h"
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#include "drv_log.h"
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#include "dmcu_pmp.h"
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#include "dmcu_dbg.h"
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#include "dmcu_hal.h"
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static PMP_ENTRY_INFO g_dmcu_pmp_entry[] = {
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{
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/* LiteOS Code READ/EXEC/NON-WRITE NOMMU SEC CACHEABLE (part 1) */
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.ucNumber = DMCU_REGION_LOS_CODE_START,
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.bLocked = TRUE,
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.accPermission.readAcc = E_MEM_RD_ACC_RD,
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.accPermission.writeAcc = E_MEM_WR_ACC_NON_WR,
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.accPermission.excuteAcc = E_MEM_EX_ACC_EX,
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.ucAddressMatch = PMP_RGN_ADDR_MATCH_OFF,
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.uwBaseAddress = 0,
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.uwRegionSize = 0,
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.memAttr = MEM_ATTR_WB_RW_ALLOC,
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.seCtl = SEC_CONTRLO_SECURE_NOMMU,
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},
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{
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/* LiteOS Code READ/EXEC/NON-WRITE NOMMU SEC CACHEABLE (part 2) */
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.ucNumber = DMCU_REGION_LOS_CODE_END,
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.bLocked = TRUE,
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.accPermission.readAcc = E_MEM_RD_ACC_RD,
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.accPermission.writeAcc = E_MEM_WR_ACC_NON_WR,
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.accPermission.excuteAcc = E_MEM_EX_ACC_EX,
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.ucAddressMatch = PMP_RGN_ADDR_MATCH_TOR,
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.uwBaseAddress = 0,
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.uwRegionSize = 0,
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.memAttr = MEM_ATTR_WB_RW_ALLOC,
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.seCtl = SEC_CONTRLO_SECURE_NOMMU,
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},
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{
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/* LiteOS Data READ/EXEC/WRITE NOMMU SEC CACHEABLE */
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.ucNumber = DMCU_REGION_LOS_DATA_END,
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.bLocked = TRUE,
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.accPermission.readAcc = E_MEM_RD_ACC_RD,
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.accPermission.writeAcc = E_MEM_WR_ACC_WR,
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.accPermission.excuteAcc = E_MEM_EX_ACC_NON_EX,
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.ucAddressMatch = PMP_RGN_ADDR_MATCH_TOR,
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.uwBaseAddress = 0,
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.uwRegionSize = 0,
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.memAttr = MEM_ATTR_WB_RW_ALLOC,
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.seCtl = SEC_CONTRLO_SECURE_NOMMU,
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},
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{
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/* NONSEC PAGE TABLE READ/EXEC/WRITE NOMMU NONSEC NONCACHEABLE */
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.ucNumber = DMCU_REGION_IOMMU_PT_NS,
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.bLocked = TRUE,
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.accPermission.readAcc = E_MEM_RD_ACC_RD,
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.accPermission.writeAcc = E_MEM_WR_ACC_WR,
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.accPermission.excuteAcc = E_MEM_EX_ACC_NON_EX,
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.ucAddressMatch = PMP_RGN_ADDR_MATCH_NAPOT,
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.uwBaseAddress = (td_u32)DMCU_NS_PT_BASEADDR,
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.uwRegionSize = 1 << 22, /* 1 << 22 is PMP_REGION_SIZE_4MB */
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.memAttr = MEM_ATTR_NORM_NON_CA_BUF,
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.seCtl = SEC_CONTRLO_NOSECURE_NOMMU,
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},
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{
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/* ITCM READ/EXEC/WRITE NOMMU SEC NONCACHEABLE */
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.ucNumber = DMCU_REGION_ITCM,
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.bLocked = FALSE, /* for resume copy itcm */
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.accPermission.readAcc = E_MEM_RD_ACC_RD,
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.accPermission.writeAcc = E_MEM_WR_ACC_NON_WR,
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.accPermission.excuteAcc = E_MEM_EX_ACC_EX,
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.ucAddressMatch = PMP_RGN_ADDR_MATCH_NAPOT,
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.uwBaseAddress = (td_u32)DMCU_ITCM_BASE_ADDR,
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.uwRegionSize = 1 << 15, /* 1 << 15 is PMP_REGION_SIZE_32KB */
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.memAttr = MEM_ATTR_NORM_NON_CA_BUF,
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.seCtl = SEC_CONTRLO_SECURE_NOMMU,
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},
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{
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/* DMCU_LOG NOMMU NONCACHEABLE */
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.ucNumber = DMCU_REGION_LOG,
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.bLocked = TRUE,
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.accPermission.readAcc = E_MEM_RD_ACC_RD,
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.accPermission.writeAcc = E_MEM_WR_ACC_WR,
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.accPermission.excuteAcc = E_MEM_EX_ACC_EX,
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.ucAddressMatch = PMP_RGN_ADDR_MATCH_NAPOT,
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.uwBaseAddress = (td_u32)DMCU_PROC_START_ADDR,
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.uwRegionSize = 1 << 20, /* 1 << 20 is PMP_REGION_SIZE_1MB */
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.memAttr = MEM_ATTR_NORM_NON_CA_BUF,
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.seCtl = SEC_CONTRLO_NOSECURE_NOMMU,
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},
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{
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/* DMCU_IPCM NOMMU NONCACHEABLE */
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.ucNumber = DMCU_REGION_IPCM,
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.bLocked = TRUE,
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.accPermission.readAcc = E_MEM_RD_ACC_RD,
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.accPermission.writeAcc = E_MEM_WR_ACC_WR,
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.accPermission.excuteAcc = E_MEM_EX_ACC_EX,
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.ucAddressMatch = PMP_RGN_ADDR_MATCH_NAPOT,
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.uwBaseAddress = (td_u32)DMCU_IPCM_NOSEC_ADDR,
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.uwRegionSize = 1 << 20, /* 1 << 20 is PMP_REGION_SIZE_1MB */
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.memAttr = MEM_ATTR_NORM_NON_CA_BUF,
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.seCtl = SEC_CONTRLO_NOSECURE_NOMMU,
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},
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};
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void dmcu_pmp_region_init(void)
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{
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PMP_ENTRY_INFO *pmp_entry;
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pmp_entry = &g_dmcu_pmp_entry[DMCU_REGION_LOS_CODE_START];
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pmp_entry->uwBaseAddress = DMCU_LOS_CODE_START;
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pmp_entry->uwRegionSize = 0;
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pmp_entry = &g_dmcu_pmp_entry[DMCU_REGION_LOS_CODE_END];
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pmp_entry->uwBaseAddress = DMCU_LOS_CODE_START + DMCU_LOS_CODE_SIZE;
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pmp_entry->uwRegionSize = 0;
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pmp_entry = &g_dmcu_pmp_entry[DMCU_REGION_LOS_DATA_END];
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pmp_entry->uwBaseAddress = DMCU_LOS_DATA_START + DMCU_LOS_DATA_SIZE;
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pmp_entry->uwRegionSize = 0;
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return;
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}
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td_s32 dmcu_pmp_region_config(void)
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{
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td_s32 i;
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td_u32 ret;
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bool error_occur = TD_FALSE;
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PMP_ENTRY_INFO *pmp_entry = NULL;
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for (i = 0; i < sizeof(g_dmcu_pmp_entry) / sizeof(g_dmcu_pmp_entry[0]); i++) {
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pmp_entry = &g_dmcu_pmp_entry[i];
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printf("pmp[%d]: uwBaseAddress:0x%x, uwRegionSize:0x%x\n", i, pmp_entry->uwBaseAddress,
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pmp_entry->uwRegionSize);
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ret = ArchProtectionRegionSet(pmp_entry);
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if (ret != TD_SUCCESS) {
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error_occur = TRUE;
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printf("set region failed 0x%x num %d\n", ret, pmp_entry->ucNumber);
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}
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}
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return (error_occur) ? TD_FAILURE : TD_SUCCESS;
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}
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td_void dmcu_itcm_resume(td_void)
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{
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td_u32 ret;
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PMP_ENTRY_INFO *pmp = TD_NULL;
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osal_printk("%s start\n", __func__);
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pmp = &g_dmcu_pmp_entry[DMCU_REGION_ITCM];
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pmp->accPermission.writeAcc = E_MEM_WR_ACC_WR;
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ret = ArchProtectionRegionSet(pmp);
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if (ret != LOS_OK) {
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osal_printk("%s set wr err\n", __func__);
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return;
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}
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if (memcpy_s((td_void *)(&__itcm_text_start), ITCM_CODE_LEN,
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(const td_void *)(&__itcm_text_load_start), (td_uintptr_t)(&__itcm_size)) != EOK) {
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osal_printk("%s memcpy err\n", __func__);
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return;
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}
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pmp = &g_dmcu_pmp_entry[DMCU_REGION_ITCM];
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pmp->accPermission.writeAcc = E_MEM_WR_ACC_NON_WR;
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ret = ArchProtectionRegionSet(pmp);
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if (ret != LOS_OK) {
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osal_printk("%s set non wr err\n", __func__);
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return;
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}
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osal_printk("%s end\n", __func__);
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return;
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}
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void dmcu_pmp_init(void)
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{
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mcu_dmcu_status *mcu_status = get_mcu_status();
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mcu_status->u32 = 0;
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ArchProtectionUnitInit(DMCU_MIN_PMP_ADDR, DMCU_MAX_PMP_ADDR);
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dmcu_pmp_region_init();
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dmcu_pmp_region_config();
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mdc_log_init();
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dmcu_hal_set_uart_pinmux();
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mcu_status->bit.pmp_init = 1;
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return;
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}
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