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607 lines
17 KiB
607 lines
17 KiB
/*
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* Copyright (C) 2011 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_LIBDEXFILE_DEX_DEX_INSTRUCTION_INL_H_
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#define ART_LIBDEXFILE_DEX_DEX_INSTRUCTION_INL_H_
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#include "dex_instruction.h"
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namespace art {
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inline constexpr size_t Instruction::SizeInCodeUnits(Format format) {
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switch (format) {
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case k10x:
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case k12x:
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case k11n:
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case k11x:
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case k10t: return 1;
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case k20t:
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case k22x:
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case k21t:
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case k21s:
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case k21h:
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case k21c:
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case k23x:
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case k22b:
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case k22t:
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case k22s:
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case k22c: return 2;
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case k32x:
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case k30t:
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case k31t:
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case k31i:
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case k31c:
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case k35c:
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case k3rc: return 3;
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case k45cc:
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case k4rcc: return 4;
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case k51l: return 5;
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case kInvalidFormat: return 0;
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}
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}
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//------------------------------------------------------------------------------
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// VRegA
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//------------------------------------------------------------------------------
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inline bool Instruction::HasVRegA() const {
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switch (FormatOf(Opcode())) {
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case k10t: return true;
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case k10x: return true;
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case k11n: return true;
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case k11x: return true;
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case k12x: return true;
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case k20t: return true;
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case k21c: return true;
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case k21h: return true;
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case k21s: return true;
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case k21t: return true;
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case k22b: return true;
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case k22c: return true;
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case k22s: return true;
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case k22t: return true;
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case k22x: return true;
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case k23x: return true;
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case k30t: return true;
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case k31c: return true;
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case k31i: return true;
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case k31t: return true;
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case k32x: return true;
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case k35c: return true;
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case k3rc: return true;
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case k45cc: return true;
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case k4rcc: return true;
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case k51l: return true;
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default: return false;
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}
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}
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inline int32_t Instruction::VRegA() const {
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return VRegA(FormatOf(Opcode()), Fetch16(0));
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}
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inline int32_t Instruction::VRegA(Format format, uint16_t inst_data) const {
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DCHECK_EQ(format, FormatOf(Opcode()));
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switch (format) {
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case k10t: return VRegA_10t(inst_data);
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case k10x: return VRegA_10x(inst_data);
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case k11n: return VRegA_11n(inst_data);
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case k11x: return VRegA_11x(inst_data);
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case k12x: return VRegA_12x(inst_data);
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case k20t: return VRegA_20t();
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case k21c: return VRegA_21c(inst_data);
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case k21h: return VRegA_21h(inst_data);
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case k21s: return VRegA_21s(inst_data);
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case k21t: return VRegA_21t(inst_data);
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case k22b: return VRegA_22b(inst_data);
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case k22c: return VRegA_22c(inst_data);
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case k22s: return VRegA_22s(inst_data);
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case k22t: return VRegA_22t(inst_data);
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case k22x: return VRegA_22x(inst_data);
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case k23x: return VRegA_23x(inst_data);
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case k30t: return VRegA_30t();
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case k31c: return VRegA_31c(inst_data);
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case k31i: return VRegA_31i(inst_data);
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case k31t: return VRegA_31t(inst_data);
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case k32x: return VRegA_32x();
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case k35c: return VRegA_35c(inst_data);
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case k3rc: return VRegA_3rc(inst_data);
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case k45cc: return VRegA_45cc(inst_data);
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case k4rcc: return VRegA_4rcc(inst_data);
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case k51l: return VRegA_51l(inst_data);
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default:
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LOG(FATAL) << "Tried to access vA of instruction " << Name() << " which has no A operand.";
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exit(EXIT_FAILURE);
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}
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}
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inline int8_t Instruction::VRegA_10t(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k10t);
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return static_cast<int8_t>(InstAA(inst_data));
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}
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inline uint8_t Instruction::VRegA_10x(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k10x);
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return InstAA(inst_data);
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}
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inline uint4_t Instruction::VRegA_11n(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k11n);
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return InstA(inst_data);
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}
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inline uint8_t Instruction::VRegA_11x(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k11x);
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return InstAA(inst_data);
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}
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inline uint4_t Instruction::VRegA_12x(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k12x);
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return InstA(inst_data);
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}
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inline int16_t Instruction::VRegA_20t() const {
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DCHECK_EQ(FormatOf(Opcode()), k20t);
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return static_cast<int16_t>(Fetch16(1));
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}
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inline uint8_t Instruction::VRegA_21c(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k21c);
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return InstAA(inst_data);
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}
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inline uint8_t Instruction::VRegA_21h(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k21h);
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return InstAA(inst_data);
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}
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inline uint8_t Instruction::VRegA_21s(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k21s);
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return InstAA(inst_data);
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}
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inline uint8_t Instruction::VRegA_21t(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k21t);
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return InstAA(inst_data);
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}
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inline uint8_t Instruction::VRegA_22b(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k22b);
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return InstAA(inst_data);
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}
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inline uint4_t Instruction::VRegA_22c(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k22c);
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return InstA(inst_data);
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}
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inline uint4_t Instruction::VRegA_22s(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k22s);
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return InstA(inst_data);
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}
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inline uint4_t Instruction::VRegA_22t(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k22t);
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return InstA(inst_data);
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}
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inline uint8_t Instruction::VRegA_22x(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k22x);
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return InstAA(inst_data);
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}
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inline uint8_t Instruction::VRegA_23x(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k23x);
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return InstAA(inst_data);
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}
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inline int32_t Instruction::VRegA_30t() const {
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DCHECK_EQ(FormatOf(Opcode()), k30t);
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return static_cast<int32_t>(Fetch32(1));
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}
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inline uint8_t Instruction::VRegA_31c(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k31c);
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return InstAA(inst_data);
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}
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inline uint8_t Instruction::VRegA_31i(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k31i);
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return InstAA(inst_data);
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}
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inline uint8_t Instruction::VRegA_31t(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k31t);
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return InstAA(inst_data);
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}
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inline uint16_t Instruction::VRegA_32x() const {
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DCHECK_EQ(FormatOf(Opcode()), k32x);
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return Fetch16(1);
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}
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inline uint4_t Instruction::VRegA_35c(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k35c);
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return InstB(inst_data); // This is labeled A in the spec.
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}
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inline uint8_t Instruction::VRegA_3rc(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k3rc);
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return InstAA(inst_data);
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}
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inline uint8_t Instruction::VRegA_51l(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k51l);
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return InstAA(inst_data);
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}
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inline uint4_t Instruction::VRegA_45cc(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k45cc);
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return InstB(inst_data); // This is labeled A in the spec.
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}
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inline uint8_t Instruction::VRegA_4rcc(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k4rcc);
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return InstAA(inst_data);
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}
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//------------------------------------------------------------------------------
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// VRegB
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//------------------------------------------------------------------------------
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inline bool Instruction::HasVRegB() const {
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switch (FormatOf(Opcode())) {
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case k11n: return true;
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case k12x: return true;
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case k21c: return true;
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case k21h: return true;
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case k21s: return true;
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case k21t: return true;
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case k22b: return true;
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case k22c: return true;
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case k22s: return true;
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case k22t: return true;
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case k22x: return true;
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case k23x: return true;
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case k31c: return true;
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case k31i: return true;
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case k31t: return true;
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case k32x: return true;
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case k35c: return true;
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case k3rc: return true;
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case k45cc: return true;
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case k4rcc: return true;
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case k51l: return true;
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default: return false;
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}
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}
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inline bool Instruction::HasWideVRegB() const {
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return FormatOf(Opcode()) == k51l;
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}
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inline int32_t Instruction::VRegB() const {
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return VRegB(FormatOf(Opcode()), Fetch16(0));
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}
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inline int32_t Instruction::VRegB(Format format, uint16_t inst_data) const {
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DCHECK_EQ(format, FormatOf(Opcode()));
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switch (format) {
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case k11n: return VRegB_11n(inst_data);
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case k12x: return VRegB_12x(inst_data);
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case k21c: return VRegB_21c();
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case k21h: return VRegB_21h();
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case k21s: return VRegB_21s();
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case k21t: return VRegB_21t();
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case k22b: return VRegB_22b();
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case k22c: return VRegB_22c(inst_data);
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case k22s: return VRegB_22s(inst_data);
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case k22t: return VRegB_22t(inst_data);
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case k22x: return VRegB_22x();
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case k23x: return VRegB_23x();
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case k31c: return VRegB_31c();
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case k31i: return VRegB_31i();
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case k31t: return VRegB_31t();
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case k32x: return VRegB_32x();
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case k35c: return VRegB_35c();
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case k3rc: return VRegB_3rc();
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case k45cc: return VRegB_45cc();
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case k4rcc: return VRegB_4rcc();
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case k51l: return VRegB_51l();
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default:
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LOG(FATAL) << "Tried to access vB of instruction " << Name() << " which has no B operand.";
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exit(EXIT_FAILURE);
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}
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}
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inline uint64_t Instruction::WideVRegB() const {
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return VRegB_51l();
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}
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inline int4_t Instruction::VRegB_11n(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k11n);
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return static_cast<int4_t>((InstB(inst_data) << 28) >> 28);
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}
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inline uint4_t Instruction::VRegB_12x(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k12x);
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return InstB(inst_data);
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}
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inline uint16_t Instruction::VRegB_21c() const {
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DCHECK_EQ(FormatOf(Opcode()), k21c);
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return Fetch16(1);
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}
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inline uint16_t Instruction::VRegB_21h() const {
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DCHECK_EQ(FormatOf(Opcode()), k21h);
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return Fetch16(1);
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}
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inline int16_t Instruction::VRegB_21s() const {
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DCHECK_EQ(FormatOf(Opcode()), k21s);
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return static_cast<int16_t>(Fetch16(1));
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}
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inline int16_t Instruction::VRegB_21t() const {
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DCHECK_EQ(FormatOf(Opcode()), k21t);
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return static_cast<int16_t>(Fetch16(1));
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}
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inline uint8_t Instruction::VRegB_22b() const {
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DCHECK_EQ(FormatOf(Opcode()), k22b);
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return static_cast<uint8_t>(Fetch16(1) & 0xff);
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}
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inline uint4_t Instruction::VRegB_22c(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k22c);
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return InstB(inst_data);
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}
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inline uint4_t Instruction::VRegB_22s(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k22s);
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return InstB(inst_data);
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}
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inline uint4_t Instruction::VRegB_22t(uint16_t inst_data) const {
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DCHECK_EQ(FormatOf(Opcode()), k22t);
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return InstB(inst_data);
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}
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inline uint16_t Instruction::VRegB_22x() const {
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DCHECK_EQ(FormatOf(Opcode()), k22x);
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return Fetch16(1);
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}
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inline uint8_t Instruction::VRegB_23x() const {
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DCHECK_EQ(FormatOf(Opcode()), k23x);
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return static_cast<uint8_t>(Fetch16(1) & 0xff);
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}
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inline uint32_t Instruction::VRegB_31c() const {
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DCHECK_EQ(FormatOf(Opcode()), k31c);
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return Fetch32(1);
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}
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inline int32_t Instruction::VRegB_31i() const {
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DCHECK_EQ(FormatOf(Opcode()), k31i);
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return static_cast<int32_t>(Fetch32(1));
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}
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inline int32_t Instruction::VRegB_31t() const {
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DCHECK_EQ(FormatOf(Opcode()), k31t);
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return static_cast<int32_t>(Fetch32(1));
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}
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inline uint16_t Instruction::VRegB_32x() const {
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DCHECK_EQ(FormatOf(Opcode()), k32x);
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return Fetch16(2);
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}
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inline uint16_t Instruction::VRegB_35c() const {
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DCHECK_EQ(FormatOf(Opcode()), k35c);
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return Fetch16(1);
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}
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inline uint16_t Instruction::VRegB_3rc() const {
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DCHECK_EQ(FormatOf(Opcode()), k3rc);
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return Fetch16(1);
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}
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inline uint16_t Instruction::VRegB_45cc() const {
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DCHECK_EQ(FormatOf(Opcode()), k45cc);
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return Fetch16(1);
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}
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inline uint16_t Instruction::VRegB_4rcc() const {
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DCHECK_EQ(FormatOf(Opcode()), k4rcc);
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return Fetch16(1);
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}
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inline uint64_t Instruction::VRegB_51l() const {
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DCHECK_EQ(FormatOf(Opcode()), k51l);
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uint64_t vB_wide = Fetch32(1) | ((uint64_t) Fetch32(3) << 32);
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return vB_wide;
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}
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//------------------------------------------------------------------------------
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// VRegC
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//------------------------------------------------------------------------------
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inline bool Instruction::HasVRegC() const {
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switch (FormatOf(Opcode())) {
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case k22b: return true;
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case k22c: return true;
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case k22s: return true;
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case k22t: return true;
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case k23x: return true;
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case k35c: return true;
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case k3rc: return true;
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case k45cc: return true;
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case k4rcc: return true;
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default: return false;
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}
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}
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inline int32_t Instruction::VRegC() const {
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return VRegC(FormatOf(Opcode()));
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}
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inline int32_t Instruction::VRegC(Format format) const {
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DCHECK_EQ(format, FormatOf(Opcode()));
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switch (format) {
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case k22b: return VRegC_22b();
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case k22c: return VRegC_22c();
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case k22s: return VRegC_22s();
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case k22t: return VRegC_22t();
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case k23x: return VRegC_23x();
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case k35c: return VRegC_35c();
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case k3rc: return VRegC_3rc();
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case k45cc: return VRegC_45cc();
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case k4rcc: return VRegC_4rcc();
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default:
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LOG(FATAL) << "Tried to access vC of instruction " << Name() << " which has no C operand.";
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exit(EXIT_FAILURE);
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}
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}
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inline int8_t Instruction::VRegC_22b() const {
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DCHECK_EQ(FormatOf(Opcode()), k22b);
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return static_cast<int8_t>(Fetch16(1) >> 8);
|
|
}
|
|
|
|
inline uint16_t Instruction::VRegC_22c() const {
|
|
DCHECK_EQ(FormatOf(Opcode()), k22c);
|
|
return Fetch16(1);
|
|
}
|
|
|
|
inline int16_t Instruction::VRegC_22s() const {
|
|
DCHECK_EQ(FormatOf(Opcode()), k22s);
|
|
return static_cast<int16_t>(Fetch16(1));
|
|
}
|
|
|
|
inline int16_t Instruction::VRegC_22t() const {
|
|
DCHECK_EQ(FormatOf(Opcode()), k22t);
|
|
return static_cast<int16_t>(Fetch16(1));
|
|
}
|
|
|
|
inline uint8_t Instruction::VRegC_23x() const {
|
|
DCHECK_EQ(FormatOf(Opcode()), k23x);
|
|
return static_cast<uint8_t>(Fetch16(1) >> 8);
|
|
}
|
|
|
|
inline uint4_t Instruction::VRegC_35c() const {
|
|
DCHECK_EQ(FormatOf(Opcode()), k35c);
|
|
return static_cast<uint4_t>(Fetch16(2) & 0x0f);
|
|
}
|
|
|
|
inline uint16_t Instruction::VRegC_3rc() const {
|
|
DCHECK_EQ(FormatOf(Opcode()), k3rc);
|
|
return Fetch16(2);
|
|
}
|
|
|
|
inline uint4_t Instruction::VRegC_45cc() const {
|
|
DCHECK_EQ(FormatOf(Opcode()), k45cc);
|
|
return static_cast<uint4_t>(Fetch16(2) & 0x0f);
|
|
}
|
|
|
|
inline uint16_t Instruction::VRegC_4rcc() const {
|
|
DCHECK_EQ(FormatOf(Opcode()), k4rcc);
|
|
return Fetch16(2);
|
|
}
|
|
|
|
//------------------------------------------------------------------------------
|
|
// VRegH
|
|
//------------------------------------------------------------------------------
|
|
inline bool Instruction::HasVRegH() const {
|
|
switch (FormatOf(Opcode())) {
|
|
case k45cc: return true;
|
|
case k4rcc: return true;
|
|
default : return false;
|
|
}
|
|
}
|
|
|
|
inline int32_t Instruction::VRegH() const {
|
|
switch (FormatOf(Opcode())) {
|
|
case k45cc: return VRegH_45cc();
|
|
case k4rcc: return VRegH_4rcc();
|
|
default :
|
|
LOG(FATAL) << "Tried to access vH of instruction " << Name() << " which has no H operand.";
|
|
exit(EXIT_FAILURE);
|
|
}
|
|
}
|
|
|
|
inline uint16_t Instruction::VRegH_45cc() const {
|
|
DCHECK_EQ(FormatOf(Opcode()), k45cc);
|
|
return Fetch16(3);
|
|
}
|
|
|
|
inline uint16_t Instruction::VRegH_4rcc() const {
|
|
DCHECK_EQ(FormatOf(Opcode()), k4rcc);
|
|
return Fetch16(3);
|
|
}
|
|
|
|
inline bool Instruction::HasVarArgs() const {
|
|
return (FormatOf(Opcode()) == k35c) || (FormatOf(Opcode()) == k45cc);
|
|
}
|
|
|
|
inline uint32_t Instruction::GetVarArgs(uint32_t arg[kMaxVarArgRegs], uint16_t inst_data) const {
|
|
DCHECK(HasVarArgs());
|
|
|
|
/*
|
|
* Note that the fields mentioned in the spec don't appear in
|
|
* their "usual" positions here compared to most formats. This
|
|
* was done so that the field names for the argument count and
|
|
* reference index match between this format and the corresponding
|
|
* range formats (3rc and friends).
|
|
*
|
|
* Bottom line: The argument count is always in vA, and the
|
|
* method constant (or equivalent) is always in vB.
|
|
*/
|
|
uint16_t regList = Fetch16(2);
|
|
uint4_t count = InstB(inst_data); // This is labeled A in the spec.
|
|
DCHECK_LE(count, 5U) << "Invalid arg count in 35c (" << count << ")";
|
|
|
|
/*
|
|
* Copy the argument registers into the arg[] array, and
|
|
* also copy the first argument (if any) into vC. (The
|
|
* DecodedInstruction structure doesn't have separate
|
|
* fields for {vD, vE, vF, vG}, so there's no need to make
|
|
* copies of those.) Note that cases 5..2 fall through.
|
|
*/
|
|
switch (count) {
|
|
case 5:
|
|
arg[4] = InstA(inst_data);
|
|
FALLTHROUGH_INTENDED;
|
|
case 4:
|
|
arg[3] = (regList >> 12) & 0x0f;
|
|
FALLTHROUGH_INTENDED;
|
|
case 3:
|
|
arg[2] = (regList >> 8) & 0x0f;
|
|
FALLTHROUGH_INTENDED;
|
|
case 2:
|
|
arg[1] = (regList >> 4) & 0x0f;
|
|
FALLTHROUGH_INTENDED;
|
|
case 1:
|
|
arg[0] = regList & 0x0f;
|
|
break;
|
|
default: // case 0
|
|
break; // Valid, but no need to do anything.
|
|
}
|
|
return count;
|
|
}
|
|
|
|
} // namespace art
|
|
|
|
#endif // ART_LIBDEXFILE_DEX_DEX_INSTRUCTION_INL_H_
|