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67 lines
2.4 KiB
67 lines
2.4 KiB
#ifndef __HLETH_MDIO_H
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#define __HLETH_MDIO_H
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#define HLETH_MDIO_FRQDIV 0
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#define HLETH_MDIO_RWCTRL 0x1100
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#define HLETH_MDIO_RO_DATA 0x1104
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#define HLETH_U_MDIO_PHYADDR 0x0108
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#define HLETH_D_MDIO_PHYADDR 0x2108
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#define HLETH_U_MDIO_RO_STAT 0x010C
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#define HLETH_D_MDIO_RO_STAT 0x210C
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#define HLETH_U_MDIO_ANEG_CTRL 0x0110
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#define HLETH_D_MDIO_ANEG_CTRL 0x2110
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#define HLETH_U_MDIO_IRQENA 0x0114
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#define HLETH_D_MDIO_IRQENA 0x2114
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#define mdio_mk_rwctl(cpu_data_in, finish, rw, phy_exaddr, frq_div, phy_regnum) \
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(((cpu_data_in) << 16) | \
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(((finish) & 0x01) << 15) | \
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(((rw) & 0x01) << 13) | \
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(((phy_exaddr) & 0x1F) << 8) | \
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(((frq_div) & 0x7) << 5) | \
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((phy_regnum) & 0x1F))
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/* hardware set bit'15 of MDIO_REG(0) if mdio ready */
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#define mdio_test_ready(priv) (hleth_readl(priv->glb_base, \
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HLETH_MDIO_RWCTRL) & (1 << 15))
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#define mdio_start_phyread(priv, phy_addr, regnum) \
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hleth_writel(priv->glb_base, \
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mdio_mk_rwctl(0, 0, 0, phy_addr, HLETH_MDIO_FRQDIV, \
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regnum), \
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HLETH_MDIO_RWCTRL)
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#define mdio_get_phyread_val(priv) (hleth_readl(priv->glb_base, \
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HLETH_MDIO_RO_DATA) & 0xFFFF)
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#define mdio_phywrite(priv, phy_addr, regnum, val) \
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hleth_writel(priv->glb_base, \
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mdio_mk_rwctl(val, 0, 1, phy_addr, HLETH_MDIO_FRQDIV, \
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regnum), \
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HLETH_MDIO_RWCTRL)
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/* write mdio registers reset value */
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#define mdio_reg_reset(priv) do { \
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hleth_writel(priv->glb_base, 0x00008000, HLETH_MDIO_RWCTRL); \
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hleth_writel(priv->glb_base, 0x00000001, HLETH_U_MDIO_PHYADDR); \
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hleth_writel(priv->glb_base, 0x00000001, HLETH_D_MDIO_PHYADDR); \
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hleth_writel(priv->glb_base, 0x04631EA9, HLETH_U_MDIO_ANEG_CTRL); \
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hleth_writel(priv->glb_base, 0x04631EA9, HLETH_D_MDIO_ANEG_CTRL); \
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hleth_writel(priv->glb_base, 0x00000000, HLETH_U_MDIO_IRQENA); \
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hleth_writel(priv->glb_base, 0x00000000, HLETH_D_MDIO_IRQENA); \
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} while (0)
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int hleth_mdiobus_driver_init(struct platform_device *pdev,
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struct hleth_netdev_priv *priv);
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void hleth_mdiobus_driver_exit(struct hleth_netdev_priv *priv);
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int hleth_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
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int hleth_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
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u16 val);
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int hleth_mdiobus_write_nodelay(struct mii_bus *bus, int phy_addr, int regnum,
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u16 val);
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#endif
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/* vim: set ts=8 sw=8 tw=78: */
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