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72 lines
1.5 KiB
72 lines
1.5 KiB
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Intel Corporation <www.intel.com>
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*/
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#ifndef __CACHE_H
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#define __CACHE_H
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struct udevice;
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/*
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* Structure for the cache controller
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*/
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struct cache_info {
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phys_addr_t base; /* Base physical address of cache device. */
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};
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struct cache_ops {
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/**
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* get_info() - Get basic cache info
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*
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* @dev: Device to check (UCLASS_CACHE)
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* @info: Place to put info
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* @return 0 if OK, -ve on error
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*/
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int (*get_info)(struct udevice *dev, struct cache_info *info);
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/**
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* enable() - Enable cache
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*
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* @dev: Device to check (UCLASS_CACHE)
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* @return 0 if OK, -ve on error
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*/
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int (*enable)(struct udevice *dev);
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/**
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* disable() - Flush and disable cache
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*
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* @dev: Device to check (UCLASS_CACHE)
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* @return 0 if OK, -ve on error
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*/
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int (*disable)(struct udevice *dev);
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};
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#define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
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/**
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* cache_get_info() - Get information about a cache controller
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*
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* @dev: Device to check (UCLASS_CACHE)
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* @info: Returns cache info
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* Return: 0 if OK, -ve on error
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*/
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int cache_get_info(struct udevice *dev, struct cache_info *info);
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/**
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* cache_enable() - Enable cache
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*
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* @dev: Device to check (UCLASS_CACHE)
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* Return: 0 if OK, -ve on error
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*/
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int cache_enable(struct udevice *dev);
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/**
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* cache_disable() - Flush and disable cache
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*
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* @dev: Device to check (UCLASS_CACHE)
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* Return: 0 if OK, -ve on error
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*/
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int cache_disable(struct udevice *dev);
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#endif
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