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273 lines
5.7 KiB
273 lines
5.7 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*
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* Peng Fan <peng.fan@nxp.com>
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*/
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#ifndef _IMX8IMAGE_H_
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#define _IMX8IMAGE_H_
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#include <image.h>
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#include <inttypes.h>
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#include "imagetool.h"
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#define __packed __attribute__((packed))
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#define IV_MAX_LEN 32
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#define HASH_MAX_LEN 64
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#define MAX_NUM_IMGS 6
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#define MAX_NUM_SRK_RECORDS 4
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#define IVT_HEADER_TAG_B0 0x87
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#define IVT_VERSION_B0 0x00
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#define IMG_FLAG_HASH_SHA256 0x000
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#define IMG_FLAG_HASH_SHA384 0x100
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#define IMG_FLAG_HASH_SHA512 0x200
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#define IMG_FLAG_ENCRYPTED_MASK 0x400
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#define IMG_FLAG_ENCRYPTED_SHIFT 0x0A
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#define IMG_FLAG_BOOTFLAGS_MASK 0xFFFF0000
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#define IMG_FLAG_BOOTFLAGS_SHIFT 0x10
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#define IMG_ARRAY_ENTRY_SIZE 128
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#define HEADER_IMG_ARRAY_OFFSET 0x10
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#define HASH_TYPE_SHA_256 256
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#define HASH_TYPE_SHA_384 384
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#define HASH_TYPE_SHA_512 512
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#define IMAGE_HASH_ALGO_DEFAULT 384
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#define IMAGE_PADDING_DEFAULT 0x1000
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#define DCD_ENTRY_ADDR_IN_SCFW 0x240
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#define CONTAINER_ALIGNMENT 0x400
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#define CONTAINER_FLAGS_DEFAULT 0x10
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#define CONTAINER_FUSE_DEFAULT 0x0
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#define SIGNATURE_BLOCK_HEADER_LENGTH 0x10
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#define MAX_NUM_OF_CONTAINER 2
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#define FIRST_CONTAINER_HEADER_LENGTH 0x400
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#define BOOT_IMG_META_MU_RID_SHIFT 10
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#define BOOT_IMG_META_PART_ID_SHIFT 20
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#define IMAGE_A35_DEFAULT_META(PART) (((PART == 0) ? \
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PARTITION_ID_AP : PART) << \
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BOOT_IMG_META_PART_ID_SHIFT | \
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SC_R_MU_0A << \
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BOOT_IMG_META_MU_RID_SHIFT | \
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SC_R_A35_0)
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#define IMAGE_A53_DEFAULT_META(PART) (((PART == 0) ? \
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PARTITION_ID_AP : PART) << \
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BOOT_IMG_META_PART_ID_SHIFT | \
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SC_R_MU_0A << \
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BOOT_IMG_META_MU_RID_SHIFT | \
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SC_R_A53_0)
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#define IMAGE_A72_DEFAULT_META(PART) (((PART == 0) ? \
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PARTITION_ID_AP : PART) << \
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BOOT_IMG_META_PART_ID_SHIFT | \
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SC_R_MU_0A << \
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BOOT_IMG_META_MU_RID_SHIFT | \
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SC_R_A72_0)
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#define IMAGE_M4_0_DEFAULT_META(PART) (((PART == 0) ? \
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PARTITION_ID_M4 : PART) << \
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BOOT_IMG_META_PART_ID_SHIFT | \
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SC_R_M4_0_MU_1A << \
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BOOT_IMG_META_MU_RID_SHIFT | \
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SC_R_M4_0_PID0)
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#define IMAGE_M4_1_DEFAULT_META(PART) (((PART == 0) ? \
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PARTITION_ID_M4 : PART) << \
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BOOT_IMG_META_PART_ID_SHIFT | \
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SC_R_M4_1_MU_1A << \
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BOOT_IMG_META_MU_RID_SHIFT | \
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SC_R_M4_1_PID0)
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#define CONTAINER_IMAGE_ARRAY_START_OFFSET 0x2000
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typedef struct {
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uint8_t version;
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uint16_t length;
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uint8_t tag;
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uint16_t srk_table_offset;
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uint16_t cert_offset;
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uint16_t blob_offset;
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uint16_t signature_offset;
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uint32_t reserved;
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} __packed sig_blk_hdr_t;
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typedef struct {
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uint32_t offset;
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uint32_t size;
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uint64_t dst;
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uint64_t entry;
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uint32_t hab_flags;
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uint32_t meta;
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uint8_t hash[HASH_MAX_LEN];
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uint8_t iv[IV_MAX_LEN];
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} __packed boot_img_t;
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typedef struct {
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uint8_t version;
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uint16_t length;
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uint8_t tag;
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uint32_t flags;
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uint16_t sw_version;
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uint8_t fuse_version;
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uint8_t num_images;
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uint16_t sig_blk_offset;
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uint16_t reserved;
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boot_img_t img[MAX_NUM_IMGS];
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sig_blk_hdr_t sig_blk_hdr;
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uint32_t sigblk_size;
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uint32_t padding;
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} __packed flash_header_v3_t;
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typedef struct {
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flash_header_v3_t fhdr[MAX_NUM_OF_CONTAINER];
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} __packed imx_header_v3_t;
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struct image_array {
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char *name;
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unsigned int core_type;
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unsigned int core_id;
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unsigned int load_addr;
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};
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enum imx8image_cmd {
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CMD_INVALID,
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CMD_BOOT_FROM,
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CMD_FUSE_VERSION,
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CMD_SW_VERSION,
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CMD_MSG_BLOCK,
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CMD_FILEOFF,
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CMD_FLAG,
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CMD_APPEND,
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CMD_PARTITION,
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CMD_SOC_TYPE,
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CMD_CONTAINER,
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CMD_IMAGE,
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CMD_DATA
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};
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enum imx8image_core_type {
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CFG_CORE_INVALID,
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CFG_SCU,
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CFG_M40,
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CFG_M41,
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CFG_A35,
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CFG_A53,
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CFG_A72
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};
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enum imx8image_fld_types {
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CFG_INVALID = -1,
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CFG_COMMAND,
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CFG_CORE_TYPE,
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CFG_IMAGE_NAME,
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CFG_LOAD_ADDR
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};
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typedef enum SOC_TYPE {
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NONE = 0,
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QX,
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QM
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} soc_type_t;
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typedef enum option_type {
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NO_IMG = 0,
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DCD,
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SCFW,
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SECO,
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M40,
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M41,
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AP,
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OUTPUT,
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SCD,
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CSF,
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FLAG,
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DEVICE,
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NEW_CONTAINER,
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APPEND,
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DATA,
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PARTITION,
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FILEOFF,
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MSG_BLOCK
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} option_type_t;
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typedef struct {
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option_type_t option;
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char *filename;
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uint64_t src;
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uint64_t dst;
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uint64_t entry;
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uint64_t ext;
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} image_t;
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#define CORE_SC 1
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#define CORE_CM4_0 2
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#define CORE_CM4_1 3
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#define CORE_CA53 4
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#define CORE_CA35 4
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#define CORE_CA72 5
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#define CORE_SECO 6
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#define SC_R_OTP 357U
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#define SC_R_DEBUG 354U
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#define SC_R_ROM_0 236U
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#define MSG_DEBUG_EN SC_R_DEBUG
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#define MSG_FUSE SC_R_OTP
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#define MSG_FIELD SC_R_ROM_0
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#define IMG_TYPE_CSF 0x01 /* CSF image type */
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#define IMG_TYPE_SCD 0x02 /* SCD image type */
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#define IMG_TYPE_EXEC 0x03 /* Executable image type */
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#define IMG_TYPE_DATA 0x04 /* Data image type */
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#define IMG_TYPE_DCD_DDR 0x05 /* DCD/DDR image type */
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#define IMG_TYPE_SECO 0x06 /* SECO image type */
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#define IMG_TYPE_PROV 0x07 /* Provisioning image type */
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#define IMG_TYPE_DEK 0x08 /* DEK validation type */
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#define IMG_TYPE_SHIFT 0
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#define IMG_TYPE_MASK 0x1f
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#define IMG_TYPE(x) (((x) & IMG_TYPE_MASK) >> IMG_TYPE_SHIFT)
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#define BOOT_IMG_FLAGS_CORE_MASK 0xF
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#define BOOT_IMG_FLAGS_CORE_SHIFT 0x04
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#define BOOT_IMG_FLAGS_CPU_RID_MASK 0x3FF0
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#define BOOT_IMG_FLAGS_CPU_RID_SHIFT 4
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#define BOOT_IMG_FLAGS_MU_RID_MASK 0xFFC000
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#define BOOT_IMG_FLAGS_MU_RID_SHIFT 14
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#define BOOT_IMG_FLAGS_PARTITION_ID_MASK 0x1F000000
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#define BOOT_IMG_FLAGS_PARTITION_ID_SHIFT 24
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/* Resource id used in scfw */
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#define SC_R_A35_0 508
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#define SC_R_A53_0 1
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#define SC_R_A72_0 6
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#define SC_R_MU_0A 213
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#define SC_R_M4_0_PID0 278
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#define SC_R_M4_0_MU_1A 297
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#define SC_R_M4_1_PID0 298
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#define SC_R_M4_1_MU_1A 317
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#define PARTITION_ID_M4 0
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#define PARTITION_ID_AP 1
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#define IMG_STACK_SIZE 32
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#define append(p, s, l) do { \
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memcpy((p), (uint8_t *)(s), (l)); (p) += (l); \
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} while (0)
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#endif
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