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420 lines
13 KiB
420 lines
13 KiB
#ifndef _R842_H_
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#define _R842_H_
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#include "td_type.h"
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//20180323 modify follow item,
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//¡]1¡^LNA TOP=5, Rfg_limit(min):„³min=2., (3) mix gain limit=10.
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//20180330 modify follow item,
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//1. 166M TF code issue, add condition to solve.(low band, mid band, high band)
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//2. R842_Sys_Sel_8296 function, R842_PAL_DK IF modify to 7100, R842_SECAM_L IF modify to 7100.
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//3. R842_PAL_DK 7M, R842_Sys_Info.HPF_COR modify to 0x0F
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//4.include 20171219 modify as follow.
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//=====================================================
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//20171219 for atv, this version modify parameter as below,
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//1.FILT5_FORCEQ auto -> man
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//2.FILT5_AUTO_COMP 3 -> 0
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//3.MIXER_AMP_LPF 1 -> 7 (>700MHz)
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//4.MIXER_GAIN_LIMIT 6 -> 12 (>700MHz)
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//=====================================================
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//20180515 for J.83B and DVBC standard (R842_Freq_Sel function)
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//1. R842_Freq_Info.BYP_LPF = 0; //bypass (R15[6]=0)
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//=====================================================
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//=====================================================
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//20180515 for R842_PAL_DK R842_SECAM_L standard (R842_Sys_Sel_8296 function)
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//1. LPF R842_PAL_DK: 8000-> 8200
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//2. LPF R842_SECAM_L: 8100-> 8200
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//=====================================================
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//=====================================================
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//20180628
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//1. ATSC Standard bug modify (parameter MIXER_AMP_LPF -> DET_BW_LPF)
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//=====================================================
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#define R842_VERSION "R842_v1.9H2"
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#define R842_VER_NUM 9
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#define R842_CHIP_ID 0x97
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#define R842_ATV_CIF_5M FALSE //by CTMR
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//----------------------------------------------------------//
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// Type Define //
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//----------------------------------------------------------//
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#define UINT8 unsigned char
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#define UINT16 unsigned short
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#define UINT32 unsigned long
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#define INT8 signed char
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#define INT16 signed short
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#define INT32 signed int
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#define TRUE 1
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#define FALSE 0
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//----------------------------------------------------------//
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// Define //
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//----------------------------------------------------------//
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#define R842_REG_NUM 48 //R0~R7: read only
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#define R842_TF_HIGH_NUM 8
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#define R842_TF_MID_NUM 11
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#define R842_TF_LOW_NUM 9
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#define R842_RING_POWER_FREQ 115000
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//#define R842_IMR_IF 5300
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#define R842_IMR_TRIAL 9
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#define R842_IMR_GAIN_REG 20
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#define R842_IMR_PHASE_REG 21
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#define R842_IMR_IQCAP_REG 19
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#define R842_IMR_POINT_NUM 8
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//----------------------------------------------------------//
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// Internal Structure //
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//----------------------------------------------------------//
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typedef struct _R842_Sys_Info_Type
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{
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UINT16 IF_KHz;
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UINT16 FILT_CAL_IF;
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UINT8 BW;
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UINT8 HPF_COR;
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UINT8 FILT_EXT_ENA;
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UINT8 FILT_EXT_POINT;
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UINT8 HPF_EXT_SEL;
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UINT8 HPF_NOTCH;
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UINT8 DET_LPF_AUTO;
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UINT8 LPF_CUR;
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UINT8 FILT3_COMP;
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UINT8 FILT5_FORCEQ;
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UINT8 FILT5_AUTO_COMP;
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UINT8 FILT5_MAN_COMP;
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UINT8 RF_LTE_PSG;
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UINT8 RFAGC_CTRL;
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UINT8 NA_PWR_DET;
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UINT8 POLY_CUR;
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}R842_Sys_Info_Type;
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typedef struct _R842_Freq_Info_Type
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{
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UINT8 RF_POLY;
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UINT8 LNA_BAND;
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UINT8 LPF_CAP;
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UINT8 LPF_NOTCH;
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UINT8 IMR_MEM_NOR;
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UINT8 IMR_MEM_REV;
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UINT8 BYP_LPF;
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UINT8 TEMP;
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}R842_Freq_Info_Type;
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typedef struct _R842_SysFreq_Info_Type
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{
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UINT8 LNA_TOP;
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UINT8 LNA_VTL_H;
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UINT8 RF_TOP;
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UINT8 RF_VTL_H;
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UINT8 RF_GAIN_LIMIT;
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UINT8 NRB_TOP;
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UINT8 NRB_BW_HPF;
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UINT8 NRB_BW_LPF;
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UINT8 MIXER_TOP;
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UINT8 MIXER_VTH;
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UINT8 MIXER_VTL;
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UINT8 MIXER_GAIN_LIMIT; //
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UINT8 FILTER_TOP;
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UINT8 FILTER_VTH;
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UINT8 FILTER_VTL;
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UINT8 LNA_RF_DIS_MODE;
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UINT8 LNA_RF_DIS_CURR;
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UINT8 LNA_DIS_SLOW_FAST;
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UINT8 LNA_RF_CHARGE;
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UINT8 RF_DIS_SLOW_FAST; //20
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UINT8 BB_DET_MODE;
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UINT8 BB_DIS_CURR;
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UINT8 MIXER_FILTER_DIS;
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UINT8 IMG_NRB_ADDER;
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UINT8 ENB_POLYG; //L
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UINT8 VGA_PIN_LVL; //L
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UINT8 VGA_PIN_DEL; //L
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UINT8 VGA_OUT_ATT; //L
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UINT8 FILT3_GAIN_MAN; //L
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UINT8 TF_MODE; //30
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UINT8 HYS_MIXTOP;
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UINT8 Q_CTRL;
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UINT8 HPF_COMP;
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UINT8 FB1_RES;
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UINT8 MIXER_AMP_LPF;
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UINT8 DET_BW_LPF;
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UINT8 ENB_ATT;
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UINT8 TEMP;
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}R842_SysFreq_Info_Type;
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typedef struct _R842_Cal_Info_Type
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{
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UINT8 FILTER_6DB; //no use
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UINT8 TF_PATH;
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UINT8 MIXER_AMP_GAIN;
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UINT8 MIXER_BUFFER_GAIN;
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UINT8 LNA_GAIN;
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UINT8 LNA_POWER;
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UINT8 RFBUF_POWER;
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UINT8 RFBUF_OUT;
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}R842_Cal_Info_Type;
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typedef struct _R842_Sect_Type
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{
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UINT8 Phase_Y;
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UINT8 Gain_X;
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UINT8 Iqcap;
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UINT8 Value;
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}R842_Sect_Type;
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typedef struct _R842_TF_Result
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{
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UINT8 TF_Set;
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UINT8 TF_Value;
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}R842_TF_Result;
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typedef enum _R842_TF_Type
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{
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R842_TF_270N_39N = 0, //270n/39n (DTV Terr)
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R842_TF_BEAD_68N, //Bead/68n (China DVB-C, DTMB, ATV)
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R842_TF_270N_27N,
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R842_TF_BEAD_27N,
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R842_TF_390N_27N,
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R842_TF_390N_39N, //only for LGIT
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R842_TF_SIZE
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}R842_TF_Type;
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typedef enum _R842_UL_TF_Type
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{
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R842_UL_USING_BEAD = 0,
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R842_UL_USING_270NH,
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R842_UL_USING_390NH,
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}R842_UL_TF_Type;
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typedef enum _R842_MID_TF_Type
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{
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R842_MID_USING_27NH = 0,
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R842_MID_USING_39NH, //39n
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R842_MID_USING_68NH, //68n
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}R842_MID_TF_Type;
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typedef enum _R842_Cal_Type
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{
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R842_IMR_CAL = 0,
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R842_IMR_LNA_CAL,
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R842_TF_MID_LNA_CAL,
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R842_TF_LNA_CAL,
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R842_LPF_CAL,
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R842_LPF_LNA_CAL
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}R842_Cal_Type;
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typedef enum _R842_Xtal_Pwr_Type
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{
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//lowest, 1.5 (0)
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//lowest, 2.0 (1)
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//low, 1.5 (2)
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//low, 2.0 (3)
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//high, 1.5 (4)
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//high, 2.0 (5)
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//highest, 1.5 (6)
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//highest, 2.0 (7)
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R842_XTAL_HIGHEST = 7,
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R842_XTAL_CHECK_SIZE = 8
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}R842_Xtal_Pwr_Type;
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typedef enum _R842_Share_Xtal_Type
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{
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R842_NO_SHARE_XTAL = 0, //normal
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R842_MASTER_TO_SLAVE_XTAL_IN, //power max, cap min
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R842_MASTER_TO_SLAVE_XTAL_OUT, //power max, cap min
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R842_SLAVE_XTAL_OUT, //xtal_gm off (R32[4:3]=2'b11), cap min
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R842_SLAVE_XTAL_IN, //no use. power max? cap?
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}R842_Share_Xtal_Type;
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typedef enum _R842_IMR_Type
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{
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R842_IMR_NOR=0,
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R842_IMR_REV,
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}R842_IMR_Type;
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typedef enum _R842_TF_Mode_Type
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{
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R842_TF_AUTO=0,
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R842_TF_PLAIN,
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R842_TF_SHARP,
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}R842_TF_Mode_Type;
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typedef enum _R842_Chip_Type //Don't modify chip list
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{
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R842_MP=0,
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R842_MT,
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//R842_MT1, //not release
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}R842_Chip_Type;
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typedef enum _R842_Poly_Type
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{
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R842_Poly_0=0,
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R842_Poly_3,
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R842_Poly_5,
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}R842_Poly_Type;
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//----------------------------------------------------------//
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// R842 Public Parameter //
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//----------------------------------------------------------//
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typedef enum _R842_ErrCode
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{
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R842_Success = TRUE,
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R842_Fail = FALSE
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}R842_ErrCode;
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typedef enum _R842_Standard_Type //Don't remove standand list!!
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{
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//ATV normal IF (prefer to use)
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R842_MN_5100 = 0, //for NTSC_MN, PAL_M (VIF=5.1M)
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R842_MN_5800, //for NTSC_MN, PAL_M (VIF=5.8M)
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R842_PAL_I, //for PAL-I (VIF=7.3M)
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R842_PAL_DK, //for PAL DK (VIF=7.3M)
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R842_PAL_B_7M, //for PAL-B 7M (VIF=6.6M)
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#if(R842_ATV_CIF_5M==TRUE)
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R842_PAL_B_7M_6800, //for PAL-B 7M (VIF=6.8M)
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#endif
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R842_PAL_BGH_8M, //for PAL G/H 8M (VIF=6.6M)
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R842_SECAM_L, //for SECAM L (VIF=7.3M)
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R842_SECAM_L1, //for SECAM L' (VIF=2.25M)
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R842_SECAM_L1_INV, //for SECAM L' (VIF=7.3M)
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#if(R842_ATV_CIF_5M==TRUE)
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//ATV CIF=5M, (not prefer to use)
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R842_MN_CIF_5M, //for NTSC_MN, PLA_M (CIF=5M, VIF=6.75M)
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R842_PAL_I_CIF_5M, //for PAL-I (CIF=5M, VIF=7.75M)
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R842_PAL_DK_CIF_5M, //for PAL DK (CIF=5M, VIF=7.75M)
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R842_PAL_B_7M_CIF_5M, //for PAL-B 7M (CIF=5M, VIF=7.25M)
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R842_PAL_BGH_8M_CIF_5M, //for PAL G/H 8M (CIF=5M, VIF=7.75M)
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R842_SECAM_L_CIF_5M, //for SECAM L (CIF=5M, VIF=7.75M)
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R842_SECAM_L1_CIF_5M, //for SECAM L' (CIF=5M, VIF=2.25M)
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R842_SECAM_L1_INV_CIF_5M, //for SECAM L' (CIF=5M, VIF=7.75M)
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#endif
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R842_ATV_SIZE,
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//DTV
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R842_DVB_T_6M = R842_ATV_SIZE,
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R842_DVB_T_7M,
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R842_DVB_T_8M,
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R842_DVB_T2_6M, //IF=4.57M
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R842_DVB_T2_7M, //IF=4.57M
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R842_DVB_T2_8M, //IF=4.57M
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R842_DVB_T2_1_7M,
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R842_DVB_T2_10M,
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R842_DVB_C_8M,
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R842_DVB_C_6M,
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R842_J83B,
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R842_ISDB_T_4063, //IF=4.063M
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R842_ISDB_T_4570, //IF=4.57M
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R842_DTMB_8M_4570, //IF=4.57M
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R842_DTMB_6M_4500, //IF=4.5M, BW=6M
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R842_ATSC,
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//DTV IF=5M
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R842_DVB_T_6M_IF_5M,
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R842_DVB_T_7M_IF_5M,
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R842_DVB_T_8M_IF_5M,
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R842_DVB_T2_6M_IF_5M,
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R842_DVB_T2_7M_IF_5M,
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R842_DVB_T2_8M_IF_5M,
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R842_DVB_T2_1_7M_IF_5M,
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R842_DVB_C_8M_IF_5M,
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R842_DVB_C_6M_IF_5M,
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R842_J83B_IF_5M,
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R842_ISDB_T_IF_5M,
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R842_ISDB_T_IF_8M,
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R842_DTMB_8M_IF_5M,
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R842_DTMB_6M_IF_5M,
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R842_ATSC_IF_5M,
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R842_FM,
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R842_STD_SIZE,
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}R842_Standard_Type;
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typedef enum _R842_RF_Gain_Type
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{
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R842_RF_AUTO = 0,
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R842_RF_MANUAL
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}R842_RF_Gain_Type;
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typedef enum _R842_Xtal_Div_Type
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{
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R842_XTAL_DIV1_11 = 0,
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R842_XTAL_DIV2_12,
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R842_XTAL_DIV2_21,
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R842_XTAL_DIV4_22
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}R842_Xtal_Div_Type;
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typedef enum _R842_IfAgc_Type
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{
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R842_IF_AGC1 = 0,
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R842_IF_AGC2
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}R842_IfAgc_Type;
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typedef struct _R842_Set_Info
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{
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UINT32 RF_KHz;
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R842_Standard_Type R842_Standard;
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R842_IfAgc_Type R842_IfAgc_Select;
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}R842_Set_Info;
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typedef struct _R842_RF_Gain_Info
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{
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UINT16 RF_gain_comb;
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UINT8 RF_gain1;
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UINT8 RF_gain2;
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UINT8 RF_gain3;
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UINT8 RF_gain4;
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}R842_RF_Gain_Info;
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typedef enum _R842_TuneMode_Type
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{
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R842_AUTO_SCAN = 0,
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R842_CHANNEL_CHANGE
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}R842_TuneMode_Type;
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typedef enum _R842_ATV_IF_Type
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{
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R842_NORMAL = 0,
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R842_8296,
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}R842_ATV_IF_Type;
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//----------------------------------------------------------//
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// R842 Public Function //
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//----------------------------------------------------------//
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#define R842_Delay_MS osal_msleep
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R842_ErrCode R842_Init(void);
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R842_ErrCode R842_SetPllData(R842_Set_Info R842_INFO); //old set frequency function, replaced by below function
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R842_ErrCode R842_SetPllData_Mode(R842_Set_Info R842_INFO, R842_TuneMode_Type R842_TuningMode); //New tuning function that can specify Channel_Change or Auto_Scan by R842_TuningMode
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R842_ErrCode R842_Standby(void);
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R842_ErrCode R842_WakeUp(void);
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R842_ErrCode R842_GetTotalRssi(UINT32 RF_Freq_Khz, R842_Standard_Type RT_Standard, INT32 *RssiDbm); //*RssiDbm is dBm*1
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R842_ErrCode R842_GetTotalRssi2(UINT32 RF_Freq_Khz, R842_Standard_Type RT_Standard, INT32 *RssiDbm); //*RssiDbm is dBm*10
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R842_ErrCode R842_SetXtalCap(UINT8 u8XtalCap);
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UINT8 R842_PLL_Lock(void);
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R842_ErrCode R842_AGC_Slow(void);
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R842_ErrCode R842_AtscMonitor(UINT32 Freq_KHz);
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R842_ErrCode R842_SetStandard(R842_Standard_Type RT_Standard);
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R842_ErrCode R842_SetFrequency(R842_Set_Info R842_INFO);
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//--------------------for GUI test--------------------------//
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R842_ErrCode R842_GetRfGain(R842_RF_Gain_Info *pR842_rf_gain);
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R842_ErrCode R842_RfGainMode(R842_RF_Gain_Type R842_RfGainType);
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R842_ErrCode R842_SetIfFreq(UINT16 IF_KHz, UINT32 RF_KHz, R842_Standard_Type u1SystemStd);
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R842_ErrCode R842_SetLpfBw(UINT8 LPF_BW);
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R842_ErrCode R842_SetLpfOffset(UINT8 LPF_Offset);
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R842_ErrCode R842_SetHpfOffset(UINT8 HPF_Offset);
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R842_ErrCode R842_SetIfLpf(UINT32 LPF_Cor_Freq);
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R842_ErrCode R842_CheckMaxGain(void);
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//--------------------Test function-----------------------//
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R842_ErrCode R842_Dump_Data(void);
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R842_ErrCode R842_RfGainCtrl(R842_RF_Gain_Type R842_RfGainType, UINT8 LnaGain, UINT8 RfGain, UINT8 MixerGain, UINT8 FilterGain);
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extern UINT8 R842_IC_Check(void);
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extern UINT8 R842_Gain_Check(void);
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extern UINT8 R842_UL_TF_Check(void);
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extern UINT8 R842_I2C_Check(void);
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extern UINT8 R842_IMR_Check(void);
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extern UINT8 R842_TF_Low_Check(UINT8 TF_Low_Type);
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extern UINT8 R842_TF_Mid_Check(UINT8 TF_Mid_Type);
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extern UINT8 R842_TF_LPF_Check(void);
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R842_ErrCode R842_GetIfRssi(UINT32 *VgaGain);
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R842_ErrCode R842_GetRfRssi(UINT32 RF_Freq_Khz, R842_Standard_Type RT_Standard, INT32 *RfGain);
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//For GUI initial use. When initial, set these two flags to FALSE and call R842_Init()
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extern UINT8 R842_Initial_done_flag;
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extern UINT8 R842_IMR_done_flag;
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R842_ErrCode R842_Xtal_Parameter_Change(UINT8 Xtal_cap_value);
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#endif |