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494 lines
12 KiB
494 lines
12 KiB
/*
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* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include "emmc_config.h"
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#include "emmc_def.h"
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#include "emmc_hal.h"
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#include "emmc_registers.h"
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#include "emmc_std.h"
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#include "micro_delay.h"
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static void emmc_little_to_big(uint8_t *p, uint32_t value)
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{
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if (p == NULL)
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return;
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p[0] = (uint8_t) (value >> 24);
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p[1] = (uint8_t) (value >> 16);
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p[2] = (uint8_t) (value >> 8);
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p[3] = (uint8_t) value;
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}
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static void emmc_softreset(void)
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{
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int32_t loop = 10000;
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int32_t retry = 1000;
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/* flag clear */
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mmc_drv_obj.during_cmd_processing = FALSE;
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mmc_drv_obj.during_transfer = FALSE;
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mmc_drv_obj.during_dma_transfer = FALSE;
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mmc_drv_obj.state_machine_blocking = FALSE;
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mmc_drv_obj.force_terminate = FALSE;
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mmc_drv_obj.dma_error_flag = FALSE;
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/* during operation ? */
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if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) == 0)
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goto reset;
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/* wait CMDSEQ = 0 */
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while (loop > 0) {
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if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) == 0)
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break; /* ready */
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loop--;
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if ((loop == 0) && (retry > 0)) {
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rcar_micro_delay(1000U); /* wait 1ms */
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loop = 10000;
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retry--;
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}
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}
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reset:
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/* reset */
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SETR_32(SOFT_RST, (GETR_32(SOFT_RST) & (~SOFT_RST_SDRST)));
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SETR_32(SOFT_RST, (GETR_32(SOFT_RST) | SOFT_RST_SDRST));
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/* initialize */
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SETR_32(SD_INFO1, 0x00000000U);
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SETR_32(SD_INFO2, SD_INFO2_CLEAR);
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SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */
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SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */
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}
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static void emmc_read_response(uint32_t *response)
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{
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uint8_t *p;
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if (response == NULL)
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return;
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/* read response */
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if (mmc_drv_obj.response_length != EMMC_MAX_RESPONSE_LENGTH) {
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*response = GETR_32(SD_RSP10); /* [39:8] */
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return;
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}
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/* CSD or CID */
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p = (uint8_t *) (response);
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emmc_little_to_big(p, ((GETR_32(SD_RSP76) << 8)
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| (GETR_32(SD_RSP54) >> 24))); /* [127:96] */
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emmc_little_to_big(p + 4, ((GETR_32(SD_RSP54) << 8)
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| (GETR_32(SD_RSP32) >> 24))); /* [95:64] */
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emmc_little_to_big(p + 8, ((GETR_32(SD_RSP32) << 8)
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| (GETR_32(SD_RSP10) >> 24))); /* [63:32] */
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emmc_little_to_big(p + 12, (GETR_32(SD_RSP10) << 8));
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}
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static EMMC_ERROR_CODE emmc_response_check(uint32_t *response,
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uint32_t error_mask)
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{
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HAL_MEMCARD_RESPONSE_TYPE response_type =
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((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK);
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if (response == NULL)
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return EMMC_ERR_PARAM;
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if (response_type == HAL_MEMCARD_RESPONSE_NONE)
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return EMMC_SUCCESS;
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if (response_type <= HAL_MEMCARD_RESPONSE_R1b) {
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/* R1 or R1b */
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mmc_drv_obj.current_state =
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(EMMC_R1_STATE) ((*response & EMMC_R1_STATE_MASK) >>
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EMMC_R1_STATE_SHIFT);
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if ((*response & error_mask) != 0) {
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if ((0x80 & *response) != 0) {
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ERROR("BL2: emmc SWITCH_ERROR\n");
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}
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return EMMC_ERR_CARD_STATUS_BIT;
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}
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return EMMC_SUCCESS;
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}
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if (response_type == HAL_MEMCARD_RESPONSE_R4) {
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if ((*response & EMMC_R4_STATUS) != 0)
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return EMMC_ERR_CARD_STATUS_BIT;
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}
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return EMMC_SUCCESS;
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}
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static void emmc_WaitCmd2Cmd_8Cycle(void)
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{
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uint32_t dataL, wait = 0;
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dataL = GETR_32(SD_CLK_CTRL);
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dataL &= 0x000000FF;
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switch (dataL) {
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case 0xFF:
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case 0x00:
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case 0x01:
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case 0x02:
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case 0x04:
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case 0x08:
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case 0x10:
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case 0x20:
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wait = 10U;
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break;
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case 0x40:
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wait = 20U;
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break;
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case 0x80:
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wait = 30U;
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break;
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}
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rcar_micro_delay(wait);
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}
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static void cmdErrSdInfo2Log(void)
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{
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ERROR("BL2: emmc ERR SD_INFO2 = 0x%x\n", mmc_drv_obj.error_info.info2);
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}
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static void emmc_data_transfer_dma(void)
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{
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mmc_drv_obj.during_dma_transfer = TRUE;
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mmc_drv_obj.dma_error_flag = FALSE;
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SETR_32(SD_INFO1_MASK, 0x00000000U);
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SETR_32(SD_INFO2_MASK, (SD_INFO2_ALL_ERR | SD_INFO2_CLEAR));
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/* DMAC setting */
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if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) {
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/* transfer complete interrupt enable */
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SETR_32(DM_CM_INFO1_MASK,
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(DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE));
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SETR_32(DM_CM_INFO2_MASK,
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(DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE));
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/* BUFF --> FIFO */
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SETR_32(DM_CM_DTRAN_MODE, (DM_CM_DTRAN_MODE_CH0 |
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DM_CM_DTRAN_MODE_BIT_WIDTH));
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} else {
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/* transfer complete interrupt enable */
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SETR_32(DM_CM_INFO1_MASK,
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(DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE));
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SETR_32(DM_CM_INFO2_MASK,
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(DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE));
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/* FIFO --> BUFF */
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SETR_32(DM_CM_DTRAN_MODE, (DM_CM_DTRAN_MODE_CH1
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| DM_CM_DTRAN_MODE_BIT_WIDTH));
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}
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SETR_32(DM_DTRAN_ADDR, (((uintptr_t) mmc_drv_obj.buff_address_virtual &
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DM_DTRAN_ADDR_WRITE_MASK)));
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SETR_32(DM_CM_DTRAN_CTRL, DM_CM_DTRAN_CTRL_START);
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}
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EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response)
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{
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EMMC_ERROR_CODE rtn_code = EMMC_SUCCESS;
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HAL_MEMCARD_RESPONSE_TYPE response_type;
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HAL_MEMCARD_COMMAND_TYPE cmd_type;
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EMMC_INT_STATE state;
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uint32_t err_not_care_flag = FALSE;
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/* parameter check */
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if (response == NULL) {
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emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR_PARAM);
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return EMMC_ERR_PARAM;
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}
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/* state check */
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if (mmc_drv_obj.clock_enable != TRUE) {
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emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR_STATE);
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return EMMC_ERR_STATE;
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}
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if (mmc_drv_obj.state_machine_blocking == TRUE) {
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emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR);
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return EMMC_ERR;
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}
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state = ESTATE_BEGIN;
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response_type =
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((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd &
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HAL_MEMCARD_RESPONSE_TYPE_MASK);
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cmd_type =
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((HAL_MEMCARD_COMMAND_TYPE) mmc_drv_obj.cmd_info.cmd &
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HAL_MEMCARD_COMMAND_TYPE_MASK);
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/* state machine */
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while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END)) {
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/* The interrupt factor flag is observed. */
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emmc_interrupt();
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/* wait interrupt */
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if (mmc_drv_obj.state_machine_blocking == TRUE)
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continue;
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switch (state) {
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case ESTATE_BEGIN:
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/* Busy check */
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if ((mmc_drv_obj.error_info.info2 & SD_INFO2_CBSY) != 0) {
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emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD,
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EMMC_ERR_CARD_BUSY);
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return EMMC_ERR_CARD_BUSY;
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}
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/* clear register */
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SETR_32(SD_INFO1, 0x00000000U);
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SETR_32(SD_INFO2, SD_INFO2_CLEAR);
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SETR_32(SD_INFO1_MASK, SD_INFO1_INFO0);
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SETR_32(SD_INFO2_MASK,
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(SD_INFO2_ALL_ERR | SD_INFO2_CLEAR));
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state = ESTATE_ISSUE_CMD;
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/* through */
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case ESTATE_ISSUE_CMD:
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/* ARG */
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SETR_32(SD_ARG, mmc_drv_obj.cmd_info.arg);
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/* issue cmd */
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SETR_32(SD_CMD, mmc_drv_obj.cmd_info.hw);
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/* Set driver flag */
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mmc_drv_obj.during_cmd_processing = TRUE;
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mmc_drv_obj.state_machine_blocking = TRUE;
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if (response_type == HAL_MEMCARD_RESPONSE_NONE) {
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state = ESTATE_NON_RESP_CMD;
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} else {
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state = ESTATE_RCV_RESP;
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}
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break;
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case ESTATE_NON_RESP_CMD:
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/* interrupt disable */
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SETR_32(SD_INFO1_MASK, 0x00000000U);
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SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR);
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/* check interrupt */
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if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) {
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/* error interrupt */
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cmdErrSdInfo2Log();
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rtn_code = EMMC_ERR_INFO2;
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state = ESTATE_ERROR;
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} else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) ==
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0) {
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/* not receive expected interrupt */
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rtn_code = EMMC_ERR_RESPONSE;
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state = ESTATE_ERROR;
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} else {
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emmc_WaitCmd2Cmd_8Cycle();
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state = ESTATE_END;
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}
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break;
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case ESTATE_RCV_RESP:
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/* interrupt disable */
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SETR_32(SD_INFO1_MASK, 0x00000000U);
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SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR);
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/* check interrupt */
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if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) {
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if ((mmc_drv_obj.get_partition_access_flag ==
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TRUE)
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&& ((mmc_drv_obj.int_event2 & SD_INFO2_ERR6)
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!= 0U)) {
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err_not_care_flag = TRUE;
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rtn_code = EMMC_ERR_CMD_TIMEOUT;
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} else {
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/* error interrupt */
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cmdErrSdInfo2Log();
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rtn_code = EMMC_ERR_INFO2;
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}
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state = ESTATE_ERROR;
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break;
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} else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) ==
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0) {
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/* not receive expected interrupt */
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rtn_code = EMMC_ERR_RESPONSE;
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state = ESTATE_ERROR;
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break;
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}
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/* read response */
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emmc_read_response(response);
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/* check response */
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rtn_code = emmc_response_check(response, error_mask);
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if (rtn_code != EMMC_SUCCESS) {
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state = ESTATE_ERROR;
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break;
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}
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if (response_type == HAL_MEMCARD_RESPONSE_R1b) {
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/* R1b */
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SETR_32(SD_INFO2_MASK,
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(SD_INFO2_ALL_ERR | SD_INFO2_CLEAR));
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state = ESTATE_RCV_RESPONSE_BUSY;
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} else {
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state = ESTATE_CHECK_RESPONSE_COMPLETE;
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}
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break;
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case ESTATE_RCV_RESPONSE_BUSY:
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/* check interrupt */
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if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) {
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/* error interrupt */
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cmdErrSdInfo2Log();
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rtn_code = EMMC_ERR_INFO2;
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state = ESTATE_ERROR;
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break;
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}
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/* DAT0 not Busy */
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if ((SD_INFO2_DAT0 & mmc_drv_obj.error_info.info2) != 0) {
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state = ESTATE_CHECK_RESPONSE_COMPLETE;
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break;
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}
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break;
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case ESTATE_CHECK_RESPONSE_COMPLETE:
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if (cmd_type >= HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE) {
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state = ESTATE_DATA_TRANSFER;
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} else {
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emmc_WaitCmd2Cmd_8Cycle();
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state = ESTATE_END;
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}
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break;
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case ESTATE_DATA_TRANSFER:
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/* ADTC command */
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mmc_drv_obj.during_transfer = TRUE;
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mmc_drv_obj.state_machine_blocking = TRUE;
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if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) {
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/* DMA */
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emmc_data_transfer_dma();
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} else {
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/* PIO */
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/* interrupt enable (FIFO read/write enable) */
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if (mmc_drv_obj.cmd_info.dir ==
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HAL_MEMCARD_WRITE) {
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SETR_32(SD_INFO2_MASK,
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(SD_INFO2_BWE | SD_INFO2_ALL_ERR
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| SD_INFO2_CLEAR));
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} else {
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SETR_32(SD_INFO2_MASK,
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(SD_INFO2_BRE | SD_INFO2_ALL_ERR
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| SD_INFO2_CLEAR));
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}
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}
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state = ESTATE_DATA_TRANSFER_COMPLETE;
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break;
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case ESTATE_DATA_TRANSFER_COMPLETE:
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/* check interrupt */
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if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) {
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/* error interrupt */
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cmdErrSdInfo2Log();
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rtn_code = EMMC_ERR_INFO2;
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state = ESTATE_TRANSFER_ERROR;
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break;
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}
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/* DMAC error ? */
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if (mmc_drv_obj.dma_error_flag == TRUE) {
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/* Error occurred in DMAC driver. */
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rtn_code = EMMC_ERR_FROM_DMAC_TRANSFER;
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state = ESTATE_TRANSFER_ERROR;
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} else if (mmc_drv_obj.during_dma_transfer == TRUE) {
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/* DMAC not finished. unknown error */
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rtn_code = EMMC_ERR;
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state = ESTATE_TRANSFER_ERROR;
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} else {
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SETR_32(SD_INFO1_MASK, SD_INFO1_INFO2);
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SETR_32(SD_INFO2_MASK,
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(SD_INFO2_ALL_ERR | SD_INFO2_CLEAR));
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mmc_drv_obj.state_machine_blocking = TRUE;
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state = ESTATE_ACCESS_END;
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}
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break;
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case ESTATE_ACCESS_END:
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/* clear flag */
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if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) {
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/* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
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SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR);
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SETR_32(SD_STOP, 0x00000000U);
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mmc_drv_obj.during_dma_transfer = FALSE;
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}
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SETR_32(SD_INFO1_MASK, 0x00000000U);
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SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR);
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SETR_32(SD_INFO1, 0x00000000U);
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SETR_32(SD_INFO2, SD_INFO2_CLEAR);
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if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO2) != 0) {
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emmc_WaitCmd2Cmd_8Cycle();
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state = ESTATE_END;
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} else {
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state = ESTATE_ERROR;
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}
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break;
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case ESTATE_TRANSFER_ERROR:
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/* The error occurred in the Data transfer. */
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if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) {
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/* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
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SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR);
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SETR_32(SD_STOP, 0x00000000U);
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mmc_drv_obj.during_dma_transfer = FALSE;
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}
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/* through */
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case ESTATE_ERROR:
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if (err_not_care_flag == TRUE) {
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mmc_drv_obj.during_cmd_processing = FALSE;
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} else {
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emmc_softreset();
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emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD,
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rtn_code);
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}
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return rtn_code;
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default:
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state = ESTATE_END;
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break;
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} /* switch (state) */
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} /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */
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/* force terminate */
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if (mmc_drv_obj.force_terminate == TRUE) {
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/* timeout timer is expired. Or, PIO data transfer error. */
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/* Timeout occurred in the DMA transfer. */
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if (mmc_drv_obj.during_dma_transfer == TRUE) {
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mmc_drv_obj.during_dma_transfer = FALSE;
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}
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ERROR("BL2: emmc exec_cmd:EMMC_ERR_FORCE_TERMINATE\n");
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emmc_softreset();
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|
|
return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */
|
|
}
|
|
|
|
/* success */
|
|
mmc_drv_obj.during_cmd_processing = FALSE;
|
|
mmc_drv_obj.during_transfer = FALSE;
|
|
|
|
return EMMC_SUCCESS;
|
|
}
|