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82 lines
1.9 KiB
82 lines
1.9 KiB
/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <neoverse_e1.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* -------------------------------------------------
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* The CPU Ops reset function for Neoverse-E1.
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* Shall clobber: x0-x19
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* -------------------------------------------------
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*/
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func neoverse_e1_reset_func
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mov x19, x30
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#if ERRATA_DSU_936184
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bl errata_dsu_936184_wa
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#endif
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ret x19
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endfunc neoverse_e1_reset_func
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func neoverse_e1_cpu_pwr_dwn
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mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1
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orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr NEOVERSE_E1_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc neoverse_e1_cpu_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Neoverse N1. Must follow AAPCS.
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*/
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func neoverse_e1_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_DSU_936184, neoverse_e1, dsu_936184
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ldp x8, x30, [sp], #16
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ret
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endfunc neoverse_e1_errata_report
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#endif
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.section .rodata.neoverse_e1_regs, "aS"
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neoverse_e1_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_e1_cpu_reg_dump
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adr x6, neoverse_e1_regs
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mrs x8, NEOVERSE_E1_ECTLR_EL1
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ret
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endfunc neoverse_e1_cpu_reg_dump
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declare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \
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neoverse_e1_reset_func, \
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neoverse_e1_cpu_pwr_dwn
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