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110 lines
2.9 KiB
110 lines
2.9 KiB
/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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#include <neoverse_n2.h>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* -------------------------------------------------
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* The CPU Ops reset function for Neoverse N2.
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* -------------------------------------------------
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*/
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func neoverse_n2_reset_func
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/* Check if the PE implements SSBS */
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mrs x0, id_aa64pfr1_el1
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tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
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b.eq 1f
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/* Disable speculative loads */
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msr SSBS, xzr
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1:
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/* Force all cacheable atomic instructions to be near */
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mrs x0, NEOVERSE_N2_CPUACTLR2_EL1
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orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
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msr NEOVERSE_N2_CPUACTLR2_EL1, x0
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, cptr_el3
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orr x0, x0, #TAM_BIT
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msr cptr_el3, x0
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
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mrs x0, cptr_el2
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orr x0, x0, #TAM_BIT
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msr cptr_el2, x0
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/* No need to enable the counters as this would be done at el3 exit */
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#endif
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#if NEOVERSE_Nx_EXTERNAL_LLC
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/* Some systems may have External LLC, core needs to be made aware */
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mrs x0, NEOVERSE_N2_CPUECTLR_EL1
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orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
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msr NEOVERSE_N2_CPUECTLR_EL1, x0
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#endif
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isb
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ret
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endfunc neoverse_n2_reset_func
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func neoverse_n2_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* No need to do cache maintenance here.
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* ---------------------------------------------
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*/
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mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1
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orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT
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msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc neoverse_n2_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Neoverse N2 cores. Must follow AAPCS.
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*/
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func neoverse_n2_errata_report
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/* No errata reported for Neoverse N2 cores */
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ret
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endfunc neoverse_n2_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides Neoverse N2 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ASCII and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_n2_regs, "aS"
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neoverse_n2_regs: /* The ASCII list of register names to be reported */
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.asciz "cpupwrctlr_el1", ""
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func neoverse_n2_cpu_reg_dump
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adr x6, neoverse_n2_regs
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mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1
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ret
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endfunc neoverse_n2_cpu_reg_dump
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declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \
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neoverse_n2_reset_func, \
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neoverse_n2_core_pwr_dwn
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