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551 lines
14 KiB
551 lines
14 KiB
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef HABANALABS_H_
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#define HABANALABS_H_
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#include <linux/types.h>
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#include <linux/ioctl.h>
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#define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000
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#define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80
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#define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144
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#define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72
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enum goya_queue_id {
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GOYA_QUEUE_ID_DMA_0 = 0,
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GOYA_QUEUE_ID_DMA_1 = 1,
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GOYA_QUEUE_ID_DMA_2 = 2,
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GOYA_QUEUE_ID_DMA_3 = 3,
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GOYA_QUEUE_ID_DMA_4 = 4,
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GOYA_QUEUE_ID_CPU_PQ = 5,
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GOYA_QUEUE_ID_MME = 6,
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GOYA_QUEUE_ID_TPC0 = 7,
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GOYA_QUEUE_ID_TPC1 = 8,
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GOYA_QUEUE_ID_TPC2 = 9,
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GOYA_QUEUE_ID_TPC3 = 10,
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GOYA_QUEUE_ID_TPC4 = 11,
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GOYA_QUEUE_ID_TPC5 = 12,
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GOYA_QUEUE_ID_TPC6 = 13,
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GOYA_QUEUE_ID_TPC7 = 14,
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GOYA_QUEUE_ID_SIZE
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};
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enum gaudi_queue_id {
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GAUDI_QUEUE_ID_DMA_0_0 = 0,
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GAUDI_QUEUE_ID_DMA_0_1 = 1,
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GAUDI_QUEUE_ID_DMA_0_2 = 2,
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GAUDI_QUEUE_ID_DMA_0_3 = 3,
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GAUDI_QUEUE_ID_DMA_1_0 = 4,
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GAUDI_QUEUE_ID_DMA_1_1 = 5,
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GAUDI_QUEUE_ID_DMA_1_2 = 6,
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GAUDI_QUEUE_ID_DMA_1_3 = 7,
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GAUDI_QUEUE_ID_CPU_PQ = 8,
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GAUDI_QUEUE_ID_DMA_2_0 = 9,
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GAUDI_QUEUE_ID_DMA_2_1 = 10,
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GAUDI_QUEUE_ID_DMA_2_2 = 11,
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GAUDI_QUEUE_ID_DMA_2_3 = 12,
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GAUDI_QUEUE_ID_DMA_3_0 = 13,
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GAUDI_QUEUE_ID_DMA_3_1 = 14,
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GAUDI_QUEUE_ID_DMA_3_2 = 15,
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GAUDI_QUEUE_ID_DMA_3_3 = 16,
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GAUDI_QUEUE_ID_DMA_4_0 = 17,
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GAUDI_QUEUE_ID_DMA_4_1 = 18,
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GAUDI_QUEUE_ID_DMA_4_2 = 19,
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GAUDI_QUEUE_ID_DMA_4_3 = 20,
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GAUDI_QUEUE_ID_DMA_5_0 = 21,
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GAUDI_QUEUE_ID_DMA_5_1 = 22,
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GAUDI_QUEUE_ID_DMA_5_2 = 23,
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GAUDI_QUEUE_ID_DMA_5_3 = 24,
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GAUDI_QUEUE_ID_DMA_6_0 = 25,
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GAUDI_QUEUE_ID_DMA_6_1 = 26,
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GAUDI_QUEUE_ID_DMA_6_2 = 27,
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GAUDI_QUEUE_ID_DMA_6_3 = 28,
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GAUDI_QUEUE_ID_DMA_7_0 = 29,
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GAUDI_QUEUE_ID_DMA_7_1 = 30,
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GAUDI_QUEUE_ID_DMA_7_2 = 31,
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GAUDI_QUEUE_ID_DMA_7_3 = 32,
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GAUDI_QUEUE_ID_MME_0_0 = 33,
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GAUDI_QUEUE_ID_MME_0_1 = 34,
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GAUDI_QUEUE_ID_MME_0_2 = 35,
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GAUDI_QUEUE_ID_MME_0_3 = 36,
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GAUDI_QUEUE_ID_MME_1_0 = 37,
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GAUDI_QUEUE_ID_MME_1_1 = 38,
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GAUDI_QUEUE_ID_MME_1_2 = 39,
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GAUDI_QUEUE_ID_MME_1_3 = 40,
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GAUDI_QUEUE_ID_TPC_0_0 = 41,
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GAUDI_QUEUE_ID_TPC_0_1 = 42,
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GAUDI_QUEUE_ID_TPC_0_2 = 43,
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GAUDI_QUEUE_ID_TPC_0_3 = 44,
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GAUDI_QUEUE_ID_TPC_1_0 = 45,
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GAUDI_QUEUE_ID_TPC_1_1 = 46,
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GAUDI_QUEUE_ID_TPC_1_2 = 47,
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GAUDI_QUEUE_ID_TPC_1_3 = 48,
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GAUDI_QUEUE_ID_TPC_2_0 = 49,
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GAUDI_QUEUE_ID_TPC_2_1 = 50,
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GAUDI_QUEUE_ID_TPC_2_2 = 51,
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GAUDI_QUEUE_ID_TPC_2_3 = 52,
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GAUDI_QUEUE_ID_TPC_3_0 = 53,
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GAUDI_QUEUE_ID_TPC_3_1 = 54,
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GAUDI_QUEUE_ID_TPC_3_2 = 55,
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GAUDI_QUEUE_ID_TPC_3_3 = 56,
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GAUDI_QUEUE_ID_TPC_4_0 = 57,
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GAUDI_QUEUE_ID_TPC_4_1 = 58,
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GAUDI_QUEUE_ID_TPC_4_2 = 59,
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GAUDI_QUEUE_ID_TPC_4_3 = 60,
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GAUDI_QUEUE_ID_TPC_5_0 = 61,
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GAUDI_QUEUE_ID_TPC_5_1 = 62,
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GAUDI_QUEUE_ID_TPC_5_2 = 63,
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GAUDI_QUEUE_ID_TPC_5_3 = 64,
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GAUDI_QUEUE_ID_TPC_6_0 = 65,
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GAUDI_QUEUE_ID_TPC_6_1 = 66,
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GAUDI_QUEUE_ID_TPC_6_2 = 67,
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GAUDI_QUEUE_ID_TPC_6_3 = 68,
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GAUDI_QUEUE_ID_TPC_7_0 = 69,
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GAUDI_QUEUE_ID_TPC_7_1 = 70,
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GAUDI_QUEUE_ID_TPC_7_2 = 71,
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GAUDI_QUEUE_ID_TPC_7_3 = 72,
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GAUDI_QUEUE_ID_NIC_0_0 = 73,
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GAUDI_QUEUE_ID_NIC_0_1 = 74,
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GAUDI_QUEUE_ID_NIC_0_2 = 75,
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GAUDI_QUEUE_ID_NIC_0_3 = 76,
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GAUDI_QUEUE_ID_NIC_1_0 = 77,
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GAUDI_QUEUE_ID_NIC_1_1 = 78,
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GAUDI_QUEUE_ID_NIC_1_2 = 79,
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GAUDI_QUEUE_ID_NIC_1_3 = 80,
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GAUDI_QUEUE_ID_NIC_2_0 = 81,
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GAUDI_QUEUE_ID_NIC_2_1 = 82,
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GAUDI_QUEUE_ID_NIC_2_2 = 83,
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GAUDI_QUEUE_ID_NIC_2_3 = 84,
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GAUDI_QUEUE_ID_NIC_3_0 = 85,
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GAUDI_QUEUE_ID_NIC_3_1 = 86,
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GAUDI_QUEUE_ID_NIC_3_2 = 87,
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GAUDI_QUEUE_ID_NIC_3_3 = 88,
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GAUDI_QUEUE_ID_NIC_4_0 = 89,
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GAUDI_QUEUE_ID_NIC_4_1 = 90,
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GAUDI_QUEUE_ID_NIC_4_2 = 91,
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GAUDI_QUEUE_ID_NIC_4_3 = 92,
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GAUDI_QUEUE_ID_NIC_5_0 = 93,
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GAUDI_QUEUE_ID_NIC_5_1 = 94,
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GAUDI_QUEUE_ID_NIC_5_2 = 95,
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GAUDI_QUEUE_ID_NIC_5_3 = 96,
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GAUDI_QUEUE_ID_NIC_6_0 = 97,
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GAUDI_QUEUE_ID_NIC_6_1 = 98,
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GAUDI_QUEUE_ID_NIC_6_2 = 99,
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GAUDI_QUEUE_ID_NIC_6_3 = 100,
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GAUDI_QUEUE_ID_NIC_7_0 = 101,
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GAUDI_QUEUE_ID_NIC_7_1 = 102,
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GAUDI_QUEUE_ID_NIC_7_2 = 103,
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GAUDI_QUEUE_ID_NIC_7_3 = 104,
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GAUDI_QUEUE_ID_NIC_8_0 = 105,
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GAUDI_QUEUE_ID_NIC_8_1 = 106,
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GAUDI_QUEUE_ID_NIC_8_2 = 107,
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GAUDI_QUEUE_ID_NIC_8_3 = 108,
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GAUDI_QUEUE_ID_NIC_9_0 = 109,
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GAUDI_QUEUE_ID_NIC_9_1 = 110,
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GAUDI_QUEUE_ID_NIC_9_2 = 111,
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GAUDI_QUEUE_ID_NIC_9_3 = 112,
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GAUDI_QUEUE_ID_SIZE
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};
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enum goya_engine_id {
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GOYA_ENGINE_ID_DMA_0 = 0,
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GOYA_ENGINE_ID_DMA_1,
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GOYA_ENGINE_ID_DMA_2,
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GOYA_ENGINE_ID_DMA_3,
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GOYA_ENGINE_ID_DMA_4,
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GOYA_ENGINE_ID_MME_0,
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GOYA_ENGINE_ID_TPC_0,
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GOYA_ENGINE_ID_TPC_1,
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GOYA_ENGINE_ID_TPC_2,
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GOYA_ENGINE_ID_TPC_3,
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GOYA_ENGINE_ID_TPC_4,
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GOYA_ENGINE_ID_TPC_5,
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GOYA_ENGINE_ID_TPC_6,
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GOYA_ENGINE_ID_TPC_7,
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GOYA_ENGINE_ID_SIZE
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};
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enum gaudi_engine_id {
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GAUDI_ENGINE_ID_DMA_0 = 0,
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GAUDI_ENGINE_ID_DMA_1,
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GAUDI_ENGINE_ID_DMA_2,
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GAUDI_ENGINE_ID_DMA_3,
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GAUDI_ENGINE_ID_DMA_4,
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GAUDI_ENGINE_ID_DMA_5,
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GAUDI_ENGINE_ID_DMA_6,
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GAUDI_ENGINE_ID_DMA_7,
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GAUDI_ENGINE_ID_MME_0,
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GAUDI_ENGINE_ID_MME_1,
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GAUDI_ENGINE_ID_MME_2,
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GAUDI_ENGINE_ID_MME_3,
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GAUDI_ENGINE_ID_TPC_0,
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GAUDI_ENGINE_ID_TPC_1,
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GAUDI_ENGINE_ID_TPC_2,
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GAUDI_ENGINE_ID_TPC_3,
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GAUDI_ENGINE_ID_TPC_4,
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GAUDI_ENGINE_ID_TPC_5,
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GAUDI_ENGINE_ID_TPC_6,
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GAUDI_ENGINE_ID_TPC_7,
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GAUDI_ENGINE_ID_NIC_0,
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GAUDI_ENGINE_ID_NIC_1,
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GAUDI_ENGINE_ID_NIC_2,
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GAUDI_ENGINE_ID_NIC_3,
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GAUDI_ENGINE_ID_NIC_4,
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GAUDI_ENGINE_ID_NIC_5,
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GAUDI_ENGINE_ID_NIC_6,
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GAUDI_ENGINE_ID_NIC_7,
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GAUDI_ENGINE_ID_NIC_8,
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GAUDI_ENGINE_ID_NIC_9,
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GAUDI_ENGINE_ID_SIZE
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};
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enum hl_device_status {
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HL_DEVICE_STATUS_OPERATIONAL,
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HL_DEVICE_STATUS_IN_RESET,
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HL_DEVICE_STATUS_MALFUNCTION,
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HL_DEVICE_STATUS_NEEDS_RESET
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};
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#define HL_INFO_HW_IP_INFO 0
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#define HL_INFO_HW_EVENTS 1
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#define HL_INFO_DRAM_USAGE 2
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#define HL_INFO_HW_IDLE 3
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#define HL_INFO_DEVICE_STATUS 4
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#define HL_INFO_DEVICE_UTILIZATION 6
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#define HL_INFO_HW_EVENTS_AGGREGATE 7
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#define HL_INFO_CLK_RATE 8
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#define HL_INFO_RESET_COUNT 9
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#define HL_INFO_TIME_SYNC 10
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#define HL_INFO_CS_COUNTERS 11
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#define HL_INFO_PCI_COUNTERS 12
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#define HL_INFO_CLK_THROTTLE_REASON 13
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#define HL_INFO_SYNC_MANAGER 14
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#define HL_INFO_TOTAL_ENERGY 15
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#define HL_INFO_PLL_FREQUENCY 16
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#define HL_INFO_VERSION_MAX_LEN 128
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#define HL_INFO_CARD_NAME_MAX_LEN 16
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struct hl_info_hw_ip_info {
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__u64 sram_base_address;
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__u64 dram_base_address;
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__u64 dram_size;
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__u32 sram_size;
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__u32 num_of_events;
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__u32 device_id;
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__u32 module_id;
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__u32 reserved;
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__u16 first_available_interrupt_id;
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__u16 reserved2;
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__u32 cpld_version;
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__u32 psoc_pci_pll_nr;
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__u32 psoc_pci_pll_nf;
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__u32 psoc_pci_pll_od;
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__u32 psoc_pci_pll_div_factor;
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__u8 tpc_enabled_mask;
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__u8 dram_enabled;
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__u8 pad[2];
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__u8 cpucp_version[HL_INFO_VERSION_MAX_LEN];
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__u8 card_name[HL_INFO_CARD_NAME_MAX_LEN];
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__u64 reserved3;
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__u64 dram_page_size;
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};
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struct hl_info_dram_usage {
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__u64 dram_free_mem;
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__u64 ctx_dram_mem;
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};
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#define HL_BUSY_ENGINES_MASK_EXT_SIZE 2
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struct hl_info_hw_idle {
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__u32 is_idle;
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__u32 busy_engines_mask;
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__u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE];
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};
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struct hl_info_device_status {
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__u32 status;
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__u32 pad;
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};
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struct hl_info_device_utilization {
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__u32 utilization;
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__u32 pad;
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};
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struct hl_info_clk_rate {
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__u32 cur_clk_rate_mhz;
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__u32 max_clk_rate_mhz;
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};
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struct hl_info_reset_count {
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__u32 hard_reset_cnt;
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__u32 soft_reset_cnt;
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};
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struct hl_info_time_sync {
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__u64 device_time;
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__u64 host_time;
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};
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struct hl_info_pci_counters {
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__u64 rx_throughput;
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__u64 tx_throughput;
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__u64 replay_cnt;
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};
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#define HL_CLK_THROTTLE_POWER 0x1
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#define HL_CLK_THROTTLE_THERMAL 0x2
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struct hl_info_clk_throttle {
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__u32 clk_throttling_reason;
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};
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struct hl_info_energy {
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__u64 total_energy_consumption;
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};
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#define HL_PLL_NUM_OUTPUTS 4
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struct hl_pll_frequency_info {
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__u16 output[HL_PLL_NUM_OUTPUTS];
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};
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struct hl_info_sync_manager {
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__u32 first_available_sync_object;
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__u32 first_available_monitor;
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__u32 first_available_cq;
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__u32 reserved;
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};
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struct hl_info_cs_counters {
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__u64 total_out_of_mem_drop_cnt;
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__u64 ctx_out_of_mem_drop_cnt;
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__u64 total_parsing_drop_cnt;
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__u64 ctx_parsing_drop_cnt;
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__u64 total_queue_full_drop_cnt;
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__u64 ctx_queue_full_drop_cnt;
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__u64 total_device_in_reset_drop_cnt;
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__u64 ctx_device_in_reset_drop_cnt;
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__u64 total_max_cs_in_flight_drop_cnt;
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__u64 ctx_max_cs_in_flight_drop_cnt;
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__u64 total_validation_drop_cnt;
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__u64 ctx_validation_drop_cnt;
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};
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enum gaudi_dcores {
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HL_GAUDI_WS_DCORE,
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HL_GAUDI_WN_DCORE,
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HL_GAUDI_EN_DCORE,
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HL_GAUDI_ES_DCORE
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};
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struct hl_info_args {
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__u64 return_pointer;
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__u32 return_size;
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__u32 op;
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union {
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__u32 dcore_id;
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__u32 ctx_id;
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__u32 period_ms;
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__u32 pll_index;
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};
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__u32 pad;
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};
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#define HL_CB_OP_CREATE 0
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#define HL_CB_OP_DESTROY 1
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#define HL_CB_OP_INFO 2
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#define HL_MAX_CB_SIZE (0x200000 - 32)
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#define HL_CB_FLAGS_MAP 0x1
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struct hl_cb_in {
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__u64 cb_handle;
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__u32 op;
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__u32 cb_size;
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__u32 ctx_id;
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__u32 flags;
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};
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struct hl_cb_out {
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union {
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__u64 cb_handle;
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struct {
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__u32 usage_cnt;
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__u32 pad;
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};
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};
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};
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union hl_cb_args {
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struct hl_cb_in in;
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struct hl_cb_out out;
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};
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#define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1
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struct hl_cs_chunk {
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union {
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__u64 cb_handle;
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__u64 signal_seq_arr;
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};
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__u32 queue_index;
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union {
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__u32 cb_size;
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__u32 num_signal_seq_arr;
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};
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__u32 cs_chunk_flags;
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__u32 collective_engine_id;
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__u32 pad[10];
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};
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#define HL_CS_FLAGS_FORCE_RESTORE 0x1
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#define HL_CS_FLAGS_SIGNAL 0x2
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#define HL_CS_FLAGS_WAIT 0x4
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#define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8
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#define HL_CS_FLAGS_TIMESTAMP 0x20
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#define HL_CS_FLAGS_STAGED_SUBMISSION 0x40
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#define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80
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#define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100
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#define HL_CS_STATUS_SUCCESS 0
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#define HL_MAX_JOBS_PER_CS 512
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struct hl_cs_in {
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__u64 chunks_restore;
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__u64 chunks_execute;
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union {
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__u64 chunks_store;
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__u64 seq;
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};
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__u32 num_chunks_restore;
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__u32 num_chunks_execute;
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__u32 num_chunks_store;
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__u32 cs_flags;
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__u32 ctx_id;
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};
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struct hl_cs_out {
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__u64 seq;
|
|
__u32 status;
|
|
__u32 pad;
|
|
};
|
|
union hl_cs_args {
|
|
struct hl_cs_in in;
|
|
struct hl_cs_out out;
|
|
};
|
|
struct hl_wait_cs_in {
|
|
__u64 seq;
|
|
__u64 timeout_us;
|
|
__u32 ctx_id;
|
|
__u32 pad;
|
|
};
|
|
#define HL_WAIT_CS_STATUS_COMPLETED 0
|
|
#define HL_WAIT_CS_STATUS_BUSY 1
|
|
#define HL_WAIT_CS_STATUS_TIMEDOUT 2
|
|
#define HL_WAIT_CS_STATUS_ABORTED 3
|
|
#define HL_WAIT_CS_STATUS_INTERRUPTED 4
|
|
#define HL_WAIT_CS_STATUS_FLAG_GONE 0x1
|
|
#define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2
|
|
struct hl_wait_cs_out {
|
|
__u32 status;
|
|
__u32 flags;
|
|
__s64 timestamp_nsec;
|
|
};
|
|
union hl_wait_cs_args {
|
|
struct hl_wait_cs_in in;
|
|
struct hl_wait_cs_out out;
|
|
};
|
|
#define HL_MEM_OP_ALLOC 0
|
|
#define HL_MEM_OP_FREE 1
|
|
#define HL_MEM_OP_MAP 2
|
|
#define HL_MEM_OP_UNMAP 3
|
|
#define HL_MEM_OP_MAP_BLOCK 4
|
|
#define HL_MEM_CONTIGUOUS 0x1
|
|
#define HL_MEM_SHARED 0x2
|
|
#define HL_MEM_USERPTR 0x4
|
|
struct hl_mem_in {
|
|
union {
|
|
struct {
|
|
__u64 mem_size;
|
|
} alloc;
|
|
struct {
|
|
__u64 handle;
|
|
} free;
|
|
struct {
|
|
__u64 hint_addr;
|
|
__u64 handle;
|
|
} map_device;
|
|
struct {
|
|
__u64 host_virt_addr;
|
|
__u64 hint_addr;
|
|
__u64 mem_size;
|
|
} map_host;
|
|
struct {
|
|
__u64 block_addr;
|
|
} map_block;
|
|
struct {
|
|
__u64 device_virt_addr;
|
|
} unmap;
|
|
};
|
|
__u32 op;
|
|
__u32 flags;
|
|
__u32 ctx_id;
|
|
__u32 pad;
|
|
};
|
|
struct hl_mem_out {
|
|
union {
|
|
__u64 device_virt_addr;
|
|
__u64 handle;
|
|
struct {
|
|
__u64 block_handle;
|
|
__u32 block_size;
|
|
__u32 pad;
|
|
};
|
|
};
|
|
};
|
|
union hl_mem_args {
|
|
struct hl_mem_in in;
|
|
struct hl_mem_out out;
|
|
};
|
|
#define HL_DEBUG_MAX_AUX_VALUES 10
|
|
struct hl_debug_params_etr {
|
|
__u64 buffer_address;
|
|
__u64 buffer_size;
|
|
__u32 sink_mode;
|
|
__u32 pad;
|
|
};
|
|
struct hl_debug_params_etf {
|
|
__u64 buffer_address;
|
|
__u64 buffer_size;
|
|
__u32 sink_mode;
|
|
__u32 pad;
|
|
};
|
|
struct hl_debug_params_stm {
|
|
__u64 he_mask;
|
|
__u64 sp_mask;
|
|
__u32 id;
|
|
__u32 frequency;
|
|
};
|
|
struct hl_debug_params_bmon {
|
|
__u64 start_addr0;
|
|
__u64 addr_mask0;
|
|
__u64 start_addr1;
|
|
__u64 addr_mask1;
|
|
__u32 bw_win;
|
|
__u32 win_capture;
|
|
__u32 id;
|
|
__u32 pad;
|
|
};
|
|
struct hl_debug_params_spmu {
|
|
__u64 event_types[HL_DEBUG_MAX_AUX_VALUES];
|
|
__u32 event_types_num;
|
|
__u32 pad;
|
|
};
|
|
#define HL_DEBUG_OP_ETR 0
|
|
#define HL_DEBUG_OP_ETF 1
|
|
#define HL_DEBUG_OP_STM 2
|
|
#define HL_DEBUG_OP_FUNNEL 3
|
|
#define HL_DEBUG_OP_BMON 4
|
|
#define HL_DEBUG_OP_SPMU 5
|
|
#define HL_DEBUG_OP_TIMESTAMP 6
|
|
#define HL_DEBUG_OP_SET_MODE 7
|
|
struct hl_debug_args {
|
|
__u64 input_ptr;
|
|
__u64 output_ptr;
|
|
__u32 input_size;
|
|
__u32 output_size;
|
|
__u32 op;
|
|
__u32 reg_idx;
|
|
__u32 enable;
|
|
__u32 ctx_id;
|
|
};
|
|
#define HL_IOCTL_INFO _IOWR('H', 0x01, struct hl_info_args)
|
|
#define HL_IOCTL_CB _IOWR('H', 0x02, union hl_cb_args)
|
|
#define HL_IOCTL_CS _IOWR('H', 0x03, union hl_cs_args)
|
|
#define HL_IOCTL_WAIT_CS _IOWR('H', 0x04, union hl_wait_cs_args)
|
|
#define HL_IOCTL_MEMORY _IOWR('H', 0x05, union hl_mem_args)
|
|
#define HL_IOCTL_DEBUG _IOWR('H', 0x06, struct hl_debug_args)
|
|
#define HL_COMMAND_START 0x01
|
|
#define HL_COMMAND_END 0x07
|
|
#endif
|