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154 lines
4.3 KiB
154 lines
4.3 KiB
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <pmc.h>
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#include <tegra_def.h>
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#define RESET_ENABLE 0x10U
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/* Module IDs used during power ungate procedure */
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static const uint32_t pmc_cpu_powergate_id[4] = {
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14, /* CPU 0 */
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9, /* CPU 1 */
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10, /* CPU 2 */
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11 /* CPU 3 */
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};
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/*******************************************************************************
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* Power ungate CPU to start the boot process. CPU reset vectors must be
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* populated before calling this function.
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******************************************************************************/
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void tegra_pmc_cpu_on(int32_t cpu)
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{
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uint32_t val;
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/*
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* Check if CPU is already power ungated
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*/
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val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);
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if ((val & (1U << pmc_cpu_powergate_id[cpu])) == 0U) {
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/*
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* The PMC deasserts the START bit when it starts the power
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* ungate process. Loop till no power toggle is in progress.
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*/
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do {
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val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE);
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} while ((val & PMC_TOGGLE_START) != 0U);
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/*
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* Start the power ungate procedure
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*/
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val = pmc_cpu_powergate_id[cpu] | PMC_TOGGLE_START;
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tegra_pmc_write_32(PMC_PWRGATE_TOGGLE, val);
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/*
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* The PMC deasserts the START bit when it starts the power
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* ungate process. Loop till powergate START bit is asserted.
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*/
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do {
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val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE);
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} while ((val & (1U << 8)) != 0U);
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/* loop till the CPU is power ungated */
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do {
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val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);
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} while ((val & (1U << pmc_cpu_powergate_id[cpu])) == 0U);
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}
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}
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/*******************************************************************************
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* Setup CPU vectors for resume from deep sleep
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******************************************************************************/
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void tegra_pmc_cpu_setup(uint64_t reset_addr)
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{
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uint32_t val;
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tegra_pmc_write_32(PMC_SECURE_SCRATCH34,
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((uint32_t)reset_addr & 0xFFFFFFFFU) | 1U);
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val = (uint32_t)(reset_addr >> 32U);
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tegra_pmc_write_32(PMC_SECURE_SCRATCH35, val & 0x7FFU);
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}
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/*******************************************************************************
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* Lock CPU vectors to restrict further writes
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******************************************************************************/
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void tegra_pmc_lock_cpu_vectors(void)
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{
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uint32_t val;
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/* lock PMC_SECURE_SCRATCH22 */
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val = tegra_pmc_read_32(PMC_SECURE_DISABLE2);
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val |= PMC_SECURE_DISABLE2_WRITE22_ON;
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tegra_pmc_write_32(PMC_SECURE_DISABLE2, val);
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/* lock PMC_SECURE_SCRATCH34/35 */
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val = tegra_pmc_read_32(PMC_SECURE_DISABLE3);
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val |= (PMC_SECURE_DISABLE3_WRITE34_ON |
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PMC_SECURE_DISABLE3_WRITE35_ON);
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tegra_pmc_write_32(PMC_SECURE_DISABLE3, val);
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}
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/*******************************************************************************
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* Find out if this is the last standing CPU
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******************************************************************************/
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bool tegra_pmc_is_last_on_cpu(void)
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{
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int i, cpu = read_mpidr() & MPIDR_CPU_MASK;
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uint32_t val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);;
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bool status = true;
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/* check if this is the last standing CPU */
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for (i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER; i++) {
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/* skip the current CPU */
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if (i == cpu)
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continue;
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/* are other CPUs already power gated? */
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if ((val & ((uint32_t)1 << pmc_cpu_powergate_id[i])) != 0U) {
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status = false;
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}
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}
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return status;
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}
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/*******************************************************************************
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* Handler to be called on exiting System suspend. Right now only DPD registers
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* are cleared.
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******************************************************************************/
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void tegra_pmc_resume(void)
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{
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/* Clear DPD sample */
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mmio_write_32((TEGRA_PMC_BASE + PMC_IO_DPD_SAMPLE), 0x0);
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/* Clear DPD Enable */
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mmio_write_32((TEGRA_PMC_BASE + PMC_DPD_ENABLE_0), 0x0);
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}
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/*******************************************************************************
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* Restart the system
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******************************************************************************/
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__dead2 void tegra_pmc_system_reset(void)
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{
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uint32_t reg;
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reg = tegra_pmc_read_32(PMC_CONFIG);
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reg |= RESET_ENABLE; /* restart */
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tegra_pmc_write_32(PMC_CONFIG, reg);
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wfi();
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ERROR("Tegra System Reset: operation not handled.\n");
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panic();
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}
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