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129 lines
3.8 KiB
129 lines
3.8 KiB
/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <drivers/arm/gicv2.h>
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#include <platform_def.h>
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.globl plat_secondary_cold_boot_setup
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.globl plat_is_my_cpu_primary
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.globl zynqmp_calc_core_pos
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.globl plat_my_core_pos
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl platform_mem_init
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* TODO: Should we read the PSYS register to make sure
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* that the request has gone through.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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mrs x0, mpidr_el1
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/* Deactivate the gic cpu interface */
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ldr x1, =BASE_GICC_BASE
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mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
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orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
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str w0, [x1, #GICC_CTLR]
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/*
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* There is no sane reason to come out of this wfi. This
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* cpu will be powered on and reset by the cpu_on pm api
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*/
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dsb sy
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1:
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no_ret plat_panic_handler
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endfunc plat_secondary_cold_boot_setup
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func plat_is_my_cpu_primary
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mov x9, x30
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bl plat_my_core_pos
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cmp x0, #ZYNQMP_PRIMARY_CPU
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cset x0, eq
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ret x9
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This function uses the zynqmp_calc_core_pos()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b zynqmp_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned int zynqmp_calc_core_pos(u_register_t mpidr)
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* Helper function to calculate the core position.
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* With this function: CorePos = (ClusterId * 4) +
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* CoreId
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* -----------------------------------------------------
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*/
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func zynqmp_calc_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc zynqmp_calc_core_pos
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0 - x4
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm x0, ZYNQMP_CRASH_UART_BASE
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mov_imm x1, ZYNQMP_CRASH_UART_CLK_IN_HZ
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mov_imm x2, ZYNQMP_UART_BAUDRATE
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b console_cdns_core_init
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(int c)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, ZYNQMP_CRASH_UART_BASE
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b console_cdns_core_putc
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endfunc plat_crash_console_putc
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/* ---------------------------------------------
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* void plat_crash_console_flush()
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* Function to force a write of all buffered
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* data that hasn't been output.
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* Out : void.
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* Clobber list : r0
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* ---------------------------------------------
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*/
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func plat_crash_console_flush
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mov_imm x0, ZYNQMP_CRASH_UART_BASE
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b console_cdns_core_flush
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endfunc plat_crash_console_flush
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/* ---------------------------------------------------------------------
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* We don't need to carry out any memory initialization on ARM
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* platforms. The Secure RAM is accessible straight away.
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* ---------------------------------------------------------------------
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*/
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func platform_mem_init
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ret
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endfunc platform_mem_init
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