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42 lines
1.1 KiB
42 lines
1.1 KiB
#ifndef __HLETH_FEPHY_FIX_H
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#define __HLETH_FEPHY_FIX_H
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#define CONFIG_CHIP_RESERVED17
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/* fephy CRG */
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#ifdef CONFIG_CHIP_RESERVED17
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#define CRG_BASE 0xF8003000
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#define HLETHPHY_SYSREG_REG 0x0510
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#elif defined(CONFIG_CHIP_RESERVED5)
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#define CRG_BASE 0xF8A22000
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#define HLETHPHY_SYSREG_REG 0x0098
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#endif
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#define HLETH_SOFT_RESET_BIT 16
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#define HLETH_CLK_ENABLE 0x1
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#define HLETH_PHY_ADDR_BIT 23
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#define MASK_PHY_ADDR 0x1F
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/* fephy ctrl reg ,set phy addr */
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#define HLETH_FEPHY_ADDR 0x0028
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#define HLETH_FEPHY_SELECT 0x8
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#define HLETH_FEPHY_LDO_CTRL 0x844
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/* DEFAULT external phy reset pin */
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#ifdef CONFIG_CHIP_RESERVED17
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#define HLETH_FEPHY_RST_BASE 0x0510
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#define HLETH_FEPHY_RST_BIT 16
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#elif defined(CONFIG_CHIP_RESERVED5)
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#define HLETH_FEPHY_RST_BASE 0x0f80
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#define HLETH_FEPHY_RST_BIT 1
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#endif
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#define MII_EXPMD 0x1D
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#define MII_EXPMA 0x1E
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/* the following two copied from phy_quirk()
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* in "./drivers/net/ethernet/hleth-sf/net.c"
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*/
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#define PHY_ID_KSZ8051MNL 0x00221550
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#define PHY_ID_KSZ8081RNB 0x00221560
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#define DEFAULT_PHY_MASK 0xfffffff0
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#endif
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