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392 lines
15 KiB
392 lines
15 KiB
/*
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* Copyright (C) 2015 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_OPTIMIZING_COMMON_ARM64_H_
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#define ART_COMPILER_OPTIMIZING_COMMON_ARM64_H_
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#include "code_generator.h"
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#include "instruction_simplifier_shared.h"
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#include "locations.h"
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#include "nodes.h"
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#include "utils/arm64/assembler_arm64.h"
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// TODO(VIXL): Make VIXL compile with -Wshadow.
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wshadow"
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#include "aarch64/disasm-aarch64.h"
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#include "aarch64/macro-assembler-aarch64.h"
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#include "aarch64/simulator-aarch64.h"
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#pragma GCC diagnostic pop
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namespace art {
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using helpers::CanFitInShifterOperand;
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using helpers::HasShifterOperand;
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namespace arm64 {
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namespace helpers {
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// Convenience helpers to ease conversion to and from VIXL operands.
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static_assert((SP == 31) && (WSP == 31) && (XZR == 32) && (WZR == 32),
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"Unexpected values for register codes.");
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inline int VIXLRegCodeFromART(int code) {
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if (code == SP) {
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return vixl::aarch64::kSPRegInternalCode;
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}
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if (code == XZR) {
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return vixl::aarch64::kZeroRegCode;
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}
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return code;
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}
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inline int ARTRegCodeFromVIXL(int code) {
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if (code == vixl::aarch64::kSPRegInternalCode) {
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return SP;
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}
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if (code == vixl::aarch64::kZeroRegCode) {
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return XZR;
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}
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return code;
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}
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inline vixl::aarch64::Register XRegisterFrom(Location location) {
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DCHECK(location.IsRegister()) << location;
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return vixl::aarch64::XRegister(VIXLRegCodeFromART(location.reg()));
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}
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inline vixl::aarch64::Register WRegisterFrom(Location location) {
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DCHECK(location.IsRegister()) << location;
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return vixl::aarch64::WRegister(VIXLRegCodeFromART(location.reg()));
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}
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inline vixl::aarch64::Register RegisterFrom(Location location, DataType::Type type) {
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DCHECK(type != DataType::Type::kVoid && !DataType::IsFloatingPointType(type)) << type;
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return type == DataType::Type::kInt64 ? XRegisterFrom(location) : WRegisterFrom(location);
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}
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inline vixl::aarch64::Register OutputRegister(HInstruction* instr) {
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return RegisterFrom(instr->GetLocations()->Out(), instr->GetType());
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}
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inline vixl::aarch64::Register InputRegisterAt(HInstruction* instr, int input_index) {
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return RegisterFrom(instr->GetLocations()->InAt(input_index),
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instr->InputAt(input_index)->GetType());
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}
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inline vixl::aarch64::VRegister DRegisterFrom(Location location) {
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DCHECK(location.IsFpuRegister()) << location;
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return vixl::aarch64::DRegister(location.reg());
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}
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inline vixl::aarch64::VRegister QRegisterFrom(Location location) {
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DCHECK(location.IsFpuRegister()) << location;
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return vixl::aarch64::QRegister(location.reg());
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}
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inline vixl::aarch64::VRegister VRegisterFrom(Location location) {
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DCHECK(location.IsFpuRegister()) << location;
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return vixl::aarch64::VRegister(location.reg());
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}
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inline vixl::aarch64::ZRegister ZRegisterFrom(Location location) {
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DCHECK(location.IsFpuRegister()) << location;
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return vixl::aarch64::ZRegister(location.reg());
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}
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inline vixl::aarch64::VRegister SRegisterFrom(Location location) {
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DCHECK(location.IsFpuRegister()) << location;
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return vixl::aarch64::SRegister(location.reg());
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}
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inline vixl::aarch64::VRegister HRegisterFrom(Location location) {
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DCHECK(location.IsFpuRegister()) << location;
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return vixl::aarch64::HRegister(location.reg());
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}
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inline vixl::aarch64::VRegister FPRegisterFrom(Location location, DataType::Type type) {
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DCHECK(DataType::IsFloatingPointType(type)) << type;
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return type == DataType::Type::kFloat64 ? DRegisterFrom(location) : SRegisterFrom(location);
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}
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inline vixl::aarch64::VRegister OutputFPRegister(HInstruction* instr) {
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return FPRegisterFrom(instr->GetLocations()->Out(), instr->GetType());
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}
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inline vixl::aarch64::VRegister InputFPRegisterAt(HInstruction* instr, int input_index) {
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return FPRegisterFrom(instr->GetLocations()->InAt(input_index),
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instr->InputAt(input_index)->GetType());
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}
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inline vixl::aarch64::CPURegister CPURegisterFrom(Location location, DataType::Type type) {
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return DataType::IsFloatingPointType(type)
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? vixl::aarch64::CPURegister(FPRegisterFrom(location, type))
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: vixl::aarch64::CPURegister(RegisterFrom(location, type));
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}
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inline vixl::aarch64::CPURegister OutputCPURegister(HInstruction* instr) {
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return DataType::IsFloatingPointType(instr->GetType())
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? static_cast<vixl::aarch64::CPURegister>(OutputFPRegister(instr))
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: static_cast<vixl::aarch64::CPURegister>(OutputRegister(instr));
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}
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inline vixl::aarch64::CPURegister InputCPURegisterAt(HInstruction* instr, int index) {
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return DataType::IsFloatingPointType(instr->InputAt(index)->GetType())
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? static_cast<vixl::aarch64::CPURegister>(InputFPRegisterAt(instr, index))
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: static_cast<vixl::aarch64::CPURegister>(InputRegisterAt(instr, index));
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}
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inline vixl::aarch64::CPURegister InputCPURegisterOrZeroRegAt(HInstruction* instr,
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int index) {
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HInstruction* input = instr->InputAt(index);
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DataType::Type input_type = input->GetType();
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if (input->IsConstant() && input->AsConstant()->IsZeroBitPattern()) {
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return (DataType::Size(input_type) >= vixl::aarch64::kXRegSizeInBytes)
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? vixl::aarch64::Register(vixl::aarch64::xzr)
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: vixl::aarch64::Register(vixl::aarch64::wzr);
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}
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return InputCPURegisterAt(instr, index);
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}
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inline int64_t Int64FromLocation(Location location) {
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return Int64FromConstant(location.GetConstant());
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}
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inline vixl::aarch64::Operand OperandFrom(Location location, DataType::Type type) {
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if (location.IsRegister()) {
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return vixl::aarch64::Operand(RegisterFrom(location, type));
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} else {
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return vixl::aarch64::Operand(Int64FromLocation(location));
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}
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}
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inline vixl::aarch64::Operand InputOperandAt(HInstruction* instr, int input_index) {
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return OperandFrom(instr->GetLocations()->InAt(input_index),
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instr->InputAt(input_index)->GetType());
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}
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inline vixl::aarch64::MemOperand StackOperandFrom(Location location) {
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return vixl::aarch64::MemOperand(vixl::aarch64::sp, location.GetStackIndex());
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}
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inline vixl::aarch64::SVEMemOperand SveStackOperandFrom(Location location) {
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return vixl::aarch64::SVEMemOperand(vixl::aarch64::sp, location.GetStackIndex());
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}
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inline vixl::aarch64::MemOperand HeapOperand(const vixl::aarch64::Register& base,
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size_t offset = 0) {
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// A heap reference must be 32bit, so fit in a W register.
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DCHECK(base.IsW());
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return vixl::aarch64::MemOperand(base.X(), offset);
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}
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inline vixl::aarch64::MemOperand HeapOperand(const vixl::aarch64::Register& base,
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const vixl::aarch64::Register& regoffset,
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vixl::aarch64::Shift shift = vixl::aarch64::LSL,
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unsigned shift_amount = 0) {
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// A heap reference must be 32bit, so fit in a W register.
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DCHECK(base.IsW());
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return vixl::aarch64::MemOperand(base.X(), regoffset, shift, shift_amount);
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}
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inline vixl::aarch64::MemOperand HeapOperand(const vixl::aarch64::Register& base,
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Offset offset) {
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return HeapOperand(base, offset.SizeValue());
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}
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inline vixl::aarch64::MemOperand HeapOperandFrom(Location location, Offset offset) {
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return HeapOperand(RegisterFrom(location, DataType::Type::kReference), offset);
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}
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inline Location LocationFrom(const vixl::aarch64::Register& reg) {
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return Location::RegisterLocation(ARTRegCodeFromVIXL(reg.GetCode()));
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}
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inline Location LocationFrom(const vixl::aarch64::VRegister& fpreg) {
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return Location::FpuRegisterLocation(fpreg.GetCode());
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}
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inline Location LocationFrom(const vixl::aarch64::ZRegister& zreg) {
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return Location::FpuRegisterLocation(zreg.GetCode());
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}
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inline vixl::aarch64::Operand OperandFromMemOperand(
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const vixl::aarch64::MemOperand& mem_op) {
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if (mem_op.IsImmediateOffset()) {
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return vixl::aarch64::Operand(mem_op.GetOffset());
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} else {
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DCHECK(mem_op.IsRegisterOffset());
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if (mem_op.GetExtend() != vixl::aarch64::NO_EXTEND) {
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return vixl::aarch64::Operand(mem_op.GetRegisterOffset(),
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mem_op.GetExtend(),
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mem_op.GetShiftAmount());
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} else if (mem_op.GetShift() != vixl::aarch64::NO_SHIFT) {
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return vixl::aarch64::Operand(mem_op.GetRegisterOffset(),
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mem_op.GetShift(),
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mem_op.GetShiftAmount());
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} else {
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LOG(FATAL) << "Should not reach here";
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UNREACHABLE();
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}
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}
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}
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inline bool AddSubCanEncodeAsImmediate(int64_t value) {
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// If `value` does not fit but `-value` does, VIXL will automatically use
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// the 'opposite' instruction.
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return vixl::aarch64::Assembler::IsImmAddSub(value)
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|| vixl::aarch64::Assembler::IsImmAddSub(-value);
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}
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inline bool Arm64CanEncodeConstantAsImmediate(HConstant* constant, HInstruction* instr) {
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int64_t value = CodeGenerator::GetInt64ValueOf(constant);
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// TODO: Improve this when IsSIMDConstantEncodable method is implemented in VIXL.
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if (instr->IsVecReplicateScalar()) {
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if (constant->IsLongConstant()) {
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return false;
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} else if (constant->IsFloatConstant()) {
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return vixl::aarch64::Assembler::IsImmFP32(constant->AsFloatConstant()->GetValue());
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} else if (constant->IsDoubleConstant()) {
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return vixl::aarch64::Assembler::IsImmFP64(constant->AsDoubleConstant()->GetValue());
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}
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return IsUint<8>(value);
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}
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// Code generation for Min/Max:
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// Cmp left_op, right_op
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// Csel dst, left_op, right_op, cond
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if (instr->IsMin() || instr->IsMax()) {
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if (constant->GetUses().HasExactlyOneElement()) {
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// If value can be encoded as immediate for the Cmp, then let VIXL handle
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// the constant generation for the Csel.
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return AddSubCanEncodeAsImmediate(value);
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}
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// These values are encodable as immediates for Cmp and VIXL will use csinc and csinv
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// with the zr register as right_op, hence no constant generation is required.
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return constant->IsZeroBitPattern() || constant->IsOne() || constant->IsMinusOne();
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}
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// For single uses we let VIXL handle the constant generation since it will
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// use registers that are not managed by the register allocator (wip0, wip1).
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if (constant->GetUses().HasExactlyOneElement()) {
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return true;
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}
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// Our code generator ensures shift distances are within an encodable range.
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if (instr->IsRor()) {
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return true;
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}
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if (instr->IsAnd() || instr->IsOr() || instr->IsXor()) {
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// Uses logical operations.
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return vixl::aarch64::Assembler::IsImmLogical(value, vixl::aarch64::kXRegSize);
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} else if (instr->IsNeg()) {
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// Uses mov -immediate.
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return vixl::aarch64::Assembler::IsImmMovn(value, vixl::aarch64::kXRegSize);
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} else {
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DCHECK(instr->IsAdd() ||
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instr->IsIntermediateAddress() ||
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instr->IsBoundsCheck() ||
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instr->IsCompare() ||
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instr->IsCondition() ||
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instr->IsSub())
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<< instr->DebugName();
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// Uses aliases of ADD/SUB instructions.
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return AddSubCanEncodeAsImmediate(value);
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}
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}
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inline Location ARM64EncodableConstantOrRegister(HInstruction* constant,
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HInstruction* instr) {
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if (constant->IsConstant()
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&& Arm64CanEncodeConstantAsImmediate(constant->AsConstant(), instr)) {
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return Location::ConstantLocation(constant->AsConstant());
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}
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return Location::RequiresRegister();
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}
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// Check if registers in art register set have the same register code in vixl. If the register
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// codes are same, we can initialize vixl register list simply by the register masks. Currently,
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// only SP/WSP and ZXR/WZR codes are different between art and vixl.
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// Note: This function is only used for debug checks.
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inline bool ArtVixlRegCodeCoherentForRegSet(uint32_t art_core_registers,
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size_t num_core,
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uint32_t art_fpu_registers,
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size_t num_fpu) {
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// The register masks won't work if the number of register is larger than 32.
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DCHECK_GE(sizeof(art_core_registers) * 8, num_core);
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DCHECK_GE(sizeof(art_fpu_registers) * 8, num_fpu);
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for (size_t art_reg_code = 0; art_reg_code < num_core; ++art_reg_code) {
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if (RegisterSet::Contains(art_core_registers, art_reg_code)) {
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if (art_reg_code != static_cast<size_t>(VIXLRegCodeFromART(art_reg_code))) {
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return false;
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}
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}
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}
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// There is no register code translation for float registers.
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return true;
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}
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inline vixl::aarch64::Shift ShiftFromOpKind(HDataProcWithShifterOp::OpKind op_kind) {
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switch (op_kind) {
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case HDataProcWithShifterOp::kASR: return vixl::aarch64::ASR;
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case HDataProcWithShifterOp::kLSL: return vixl::aarch64::LSL;
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case HDataProcWithShifterOp::kLSR: return vixl::aarch64::LSR;
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default:
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LOG(FATAL) << "Unexpected op kind " << op_kind;
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UNREACHABLE();
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return vixl::aarch64::NO_SHIFT;
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}
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}
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inline vixl::aarch64::Extend ExtendFromOpKind(HDataProcWithShifterOp::OpKind op_kind) {
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switch (op_kind) {
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case HDataProcWithShifterOp::kUXTB: return vixl::aarch64::UXTB;
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case HDataProcWithShifterOp::kUXTH: return vixl::aarch64::UXTH;
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case HDataProcWithShifterOp::kUXTW: return vixl::aarch64::UXTW;
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case HDataProcWithShifterOp::kSXTB: return vixl::aarch64::SXTB;
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case HDataProcWithShifterOp::kSXTH: return vixl::aarch64::SXTH;
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case HDataProcWithShifterOp::kSXTW: return vixl::aarch64::SXTW;
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default:
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LOG(FATAL) << "Unexpected op kind " << op_kind;
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UNREACHABLE();
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return vixl::aarch64::NO_EXTEND;
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}
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}
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inline bool ShifterOperandSupportsExtension(HInstruction* instruction) {
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DCHECK(HasShifterOperand(instruction, InstructionSet::kArm64));
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// Although the `neg` instruction is an alias of the `sub` instruction, `HNeg`
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// does *not* support extension. This is because the `extended register` form
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// of the `sub` instruction interprets the left register with code 31 as the
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// stack pointer and not the zero register. (So does the `immediate` form.) In
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// the other form `shifted register, the register with code 31 is interpreted
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// as the zero register.
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return instruction->IsAdd() || instruction->IsSub();
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}
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inline bool IsConstantZeroBitPattern(const HInstruction* instruction) {
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return instruction->IsConstant() && instruction->AsConstant()->IsZeroBitPattern();
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}
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} // namespace helpers
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} // namespace arm64
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} // namespace art
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#endif // ART_COMPILER_OPTIMIZING_COMMON_ARM64_H_
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