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408 lines
14 KiB
408 lines
14 KiB
%def const(helper="UndefinedConstHandler"):
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/* const/class vAA, type@BBBB */
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/* const/method-handle vAA, method_handle@BBBB */
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/* const/method-type vAA, proto@BBBB */
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/* const/string vAA, string@@BBBB */
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.extern $helper
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EXPORT_PC
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FETCH w0, 1 // w0<- BBBB
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lsr w1, wINST, #8 // w1<- AA
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add x2, xFP, #OFF_FP_SHADOWFRAME
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mov x3, xSELF
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bl $helper // (index, tgt_reg, shadow_frame, self)
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PREFETCH_INST 2 // load rINST
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cbnz w0, MterpPossibleException // let reference interpreter deal with it.
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ADVANCE 2 // advance rPC
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GET_INST_OPCODE ip // extract opcode from rINST
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GOTO_OPCODE ip // jump to next instruction
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%def unused():
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/*
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* Bail to reference interpreter to throw.
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*/
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b MterpFallback
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%def op_const():
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/* const vAA, #+BBBBbbbb */
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lsr w3, wINST, #8 // w3<- AA
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FETCH w0, 1 // w0<- bbbb (low
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FETCH w1, 2 // w1<- BBBB (high
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FETCH_ADVANCE_INST 3 // advance rPC, load wINST
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orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
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GET_INST_OPCODE ip // extract opcode from wINST
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SET_VREG w0, w3 // vAA<- w0
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GOTO_OPCODE ip // jump to next instruction
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%def op_const_16():
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/* const/16 vAA, #+BBBB */
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FETCH_S w0, 1 // w0<- ssssBBBB (sign-extended)
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lsr w3, wINST, #8 // w3<- AA
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FETCH_ADVANCE_INST 2 // advance xPC, load wINST
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SET_VREG w0, w3 // vAA<- w0
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GET_INST_OPCODE ip // extract opcode from wINST
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GOTO_OPCODE ip // jump to next instruction
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%def op_const_4():
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/* const/4 vA, #+B */
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sbfx w1, wINST, #12, #4 // w1<- sssssssB
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ubfx w0, wINST, #8, #4 // w0<- A
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FETCH_ADVANCE_INST 1 // advance xPC, load wINST
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GET_INST_OPCODE ip // ip<- opcode from xINST
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SET_VREG w1, w0 // fp[A]<- w1
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GOTO_OPCODE ip // execute next instruction
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%def op_const_class():
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% const(helper="MterpConstClass")
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%def op_const_high16():
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/* const/high16 vAA, #+BBBB0000 */
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FETCH w0, 1 // r0<- 0000BBBB (zero-extended)
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lsr w3, wINST, #8 // r3<- AA
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lsl w0, w0, #16 // r0<- BBBB0000
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FETCH_ADVANCE_INST 2 // advance rPC, load rINST
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SET_VREG w0, w3 // vAA<- r0
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GET_INST_OPCODE ip // extract opcode from rINST
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GOTO_OPCODE ip // jump to next instruction
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%def op_const_method_handle():
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% const(helper="MterpConstMethodHandle")
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%def op_const_method_type():
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% const(helper="MterpConstMethodType")
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%def op_const_string():
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% const(helper="MterpConstString")
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%def op_const_string_jumbo():
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/* const/string vAA, String//BBBBBBBB */
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EXPORT_PC
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FETCH w0, 1 // w0<- bbbb (low
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FETCH w2, 2 // w2<- BBBB (high
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lsr w1, wINST, #8 // w1<- AA
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orr w0, w0, w2, lsl #16 // w1<- BBBBbbbb
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add x2, xFP, #OFF_FP_SHADOWFRAME
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mov x3, xSELF
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bl MterpConstString // (index, tgt_reg, shadow_frame, self)
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PREFETCH_INST 3 // advance rPC
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cbnz w0, MterpPossibleException // let reference interpreter deal with it.
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ADVANCE 3 // advance rPC
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GET_INST_OPCODE ip // extract opcode from rINST
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GOTO_OPCODE ip // jump to next instruction
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%def op_const_wide():
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/* const-wide vAA, #+HHHHhhhhBBBBbbbb */
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FETCH w0, 1 // w0<- bbbb (low)
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FETCH w1, 2 // w1<- BBBB (low middle)
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FETCH w2, 3 // w2<- hhhh (high middle)
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FETCH w3, 4 // w3<- HHHH (high)
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lsr w4, wINST, #8 // r4<- AA
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FETCH_ADVANCE_INST 5 // advance rPC, load wINST
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GET_INST_OPCODE ip // extract opcode from wINST
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orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
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orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb
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orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb
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SET_VREG_WIDE x0, w4
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GOTO_OPCODE ip // jump to next instruction
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%def op_const_wide_16():
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/* const-wide/16 vAA, #+BBBB */
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FETCH_S x0, 1 // x0<- ssssssssssssBBBB (sign-extended)
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lsr w3, wINST, #8 // w3<- AA
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FETCH_ADVANCE_INST 2 // advance rPC, load rINST
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GET_INST_OPCODE ip // extract opcode from rINST
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SET_VREG_WIDE x0, w3
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GOTO_OPCODE ip // jump to next instruction
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%def op_const_wide_32():
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/* const-wide/32 vAA, #+BBBBbbbb */
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FETCH w0, 1 // x0<- 000000000000bbbb (low)
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lsr w3, wINST, #8 // w3<- AA
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FETCH_S x2, 2 // x2<- ssssssssssssBBBB (high)
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FETCH_ADVANCE_INST 3 // advance rPC, load wINST
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GET_INST_OPCODE ip // extract opcode from wINST
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orr x0, x0, x2, lsl #16 // x0<- ssssssssBBBBbbbb
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SET_VREG_WIDE x0, w3
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GOTO_OPCODE ip // jump to next instruction
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%def op_const_wide_high16():
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/* const-wide/high16 vAA, #+BBBB000000000000 */
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FETCH w0, 1 // w0<- 0000BBBB (zero-extended)
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lsr w1, wINST, #8 // w1<- AA
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FETCH_ADVANCE_INST 2 // advance rPC, load wINST
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lsl x0, x0, #48
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SET_VREG_WIDE x0, w1
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GET_INST_OPCODE ip // extract opcode from wINST
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GOTO_OPCODE ip // jump to next instruction
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%def op_monitor_enter():
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/*
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* Synchronize on an object.
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*/
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/* monitor-enter vAA */
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EXPORT_PC
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lsr w2, wINST, #8 // w2<- AA
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GET_VREG w0, w2 // w0<- vAA (object)
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mov x1, xSELF // w1<- self
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bl artLockObjectFromCode
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cbnz w0, MterpException
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FETCH_ADVANCE_INST 1
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ldr w0, [xSELF, #THREAD_USE_MTERP_OFFSET]
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cbz w0, MterpFallback
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GET_INST_OPCODE ip // extract opcode from rINST
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GOTO_OPCODE ip // jump to next instruction
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%def op_monitor_exit():
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/*
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* Unlock an object.
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*
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* Exceptions that occur when unlocking a monitor need to appear as
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* if they happened at the following instruction. See the Dalvik
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* instruction spec.
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*/
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/* monitor-exit vAA */
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EXPORT_PC
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lsr w2, wINST, #8 // w2<- AA
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GET_VREG w0, w2 // w0<- vAA (object)
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mov x1, xSELF // w0<- self
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bl artUnlockObjectFromCode // w0<- success for unlock(self, obj)
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cbnz w0, MterpException
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FETCH_ADVANCE_INST 1 // before throw: advance rPC, load rINST
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ldr w0, [xSELF, #THREAD_USE_MTERP_OFFSET]
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cbz w0, MterpFallback
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GET_INST_OPCODE ip // extract opcode from rINST
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GOTO_OPCODE ip // jump to next instruction
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%def op_move(is_object="0"):
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/* for move, move-object, long-to-int */
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/* op vA, vB */
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lsr w1, wINST, #12 // x1<- B from 15:12
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ubfx w0, wINST, #8, #4 // x0<- A from 11:8
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FETCH_ADVANCE_INST 1 // advance rPC, load wINST
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GET_VREG w2, w1 // x2<- fp[B]
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GET_INST_OPCODE ip // ip<- opcode from wINST
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.if $is_object
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SET_VREG_OBJECT w2, w0 // fp[A]<- x2
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.else
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SET_VREG w2, w0 // fp[A]<- x2
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.endif
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GOTO_OPCODE ip // execute next instruction
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%def op_move_16(is_object="0"):
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/* for: move/16, move-object/16 */
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/* op vAAAA, vBBBB */
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FETCH w1, 2 // w1<- BBBB
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FETCH w0, 1 // w0<- AAAA
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FETCH_ADVANCE_INST 3 // advance xPC, load xINST
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GET_VREG w2, w1 // w2<- fp[BBBB]
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GET_INST_OPCODE ip // extract opcode from xINST
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.if $is_object
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SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2
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.else
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SET_VREG w2, w0 // fp[AAAA]<- w2
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.endif
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GOTO_OPCODE ip // jump to next instruction
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%def op_move_exception():
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/* move-exception vAA */
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lsr w2, wINST, #8 // w2<- AA
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ldr x3, [xSELF, #THREAD_EXCEPTION_OFFSET]
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mov x1, #0 // w1<- 0
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FETCH_ADVANCE_INST 1 // advance rPC, load rINST
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SET_VREG_OBJECT w3, w2 // fp[AA]<- exception obj
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GET_INST_OPCODE ip // extract opcode from rINST
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str x1, [xSELF, #THREAD_EXCEPTION_OFFSET] // clear exception
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GOTO_OPCODE ip // jump to next instruction
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%def op_move_from16(is_object="0"):
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/* for: move/from16, move-object/from16 */
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/* op vAA, vBBBB */
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FETCH w1, 1 // r1<- BBBB
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lsr w0, wINST, #8 // r0<- AA
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FETCH_ADVANCE_INST 2 // advance rPC, load wINST
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GET_VREG w2, w1 // r2<- fp[BBBB]
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GET_INST_OPCODE ip // extract opcode from wINST
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.if $is_object
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SET_VREG_OBJECT w2, w0 // fp[AA]<- r2
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.else
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SET_VREG w2, w0 // fp[AA]<- r2
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.endif
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GOTO_OPCODE ip // jump to next instruction
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%def op_move_object():
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% op_move(is_object="1")
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%def op_move_object_16():
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% op_move_16(is_object="1")
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%def op_move_object_from16():
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% op_move_from16(is_object="1")
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%def op_move_result(is_object="0"):
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/* for: move-result, move-result-object */
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/* op vAA */
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lsr w2, wINST, #8 // r2<- AA
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FETCH_ADVANCE_INST 1 // advance rPC, load wINST
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ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType.
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ldr w0, [x0] // r0 <- result.i.
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GET_INST_OPCODE ip // extract opcode from wINST
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.if $is_object
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SET_VREG_OBJECT w0, w2, w1 // fp[AA]<- r0
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.else
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SET_VREG w0, w2 // fp[AA]<- r0
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.endif
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GOTO_OPCODE ip // jump to next instruction
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%def op_move_result_object():
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% op_move_result(is_object="1")
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%def op_move_result_wide():
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/* for: move-result-wide */
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/* op vAA */
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lsr w2, wINST, #8 // r2<- AA
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FETCH_ADVANCE_INST 1 // advance rPC, load wINST
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ldr x0, [xFP, #OFF_FP_RESULT_REGISTER] // get pointer to result JType.
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ldr x0, [x0] // r0 <- result.i.
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GET_INST_OPCODE ip // extract opcode from wINST
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SET_VREG_WIDE x0, w2 // fp[AA]<- r0
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GOTO_OPCODE ip // jump to next instruction
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%def op_move_wide():
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/* move-wide vA, vB */
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/* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
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lsr w3, wINST, #12 // w3<- B
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ubfx w2, wINST, #8, #4 // w2<- A
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GET_VREG_WIDE x3, w3
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FETCH_ADVANCE_INST 1 // advance rPC, load wINST
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GET_INST_OPCODE ip // extract opcode from wINST
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SET_VREG_WIDE x3, w2
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GOTO_OPCODE ip // jump to next instruction
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%def op_move_wide_16():
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/* move-wide/16 vAAAA, vBBBB */
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/* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
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FETCH w3, 2 // w3<- BBBB
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FETCH w2, 1 // w2<- AAAA
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GET_VREG_WIDE x3, w3
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FETCH_ADVANCE_INST 3 // advance rPC, load rINST
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SET_VREG_WIDE x3, w2
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GET_INST_OPCODE ip // extract opcode from rINST
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GOTO_OPCODE ip // jump to next instruction
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%def op_move_wide_from16():
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/* move-wide/from16 vAA, vBBBB */
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/* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */
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FETCH w3, 1 // w3<- BBBB
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lsr w2, wINST, #8 // w2<- AA
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GET_VREG_WIDE x3, w3
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FETCH_ADVANCE_INST 2 // advance rPC, load wINST
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GET_INST_OPCODE ip // extract opcode from wINST
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SET_VREG_WIDE x3, w2
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GOTO_OPCODE ip // jump to next instruction
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%def op_nop():
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FETCH_ADVANCE_INST 1 // advance to next instr, load rINST
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GET_INST_OPCODE ip // ip<- opcode from rINST
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GOTO_OPCODE ip // execute it
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%def op_unused_3e():
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% unused()
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%def op_unused_3f():
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% unused()
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%def op_unused_40():
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% unused()
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%def op_unused_41():
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% unused()
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%def op_unused_42():
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% unused()
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%def op_unused_43():
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% unused()
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%def op_unused_73():
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% unused()
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%def op_unused_79():
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% unused()
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%def op_unused_7a():
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% unused()
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%def op_unused_e3():
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% unused()
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%def op_unused_e4():
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% unused()
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%def op_unused_e5():
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% unused()
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%def op_unused_e6():
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% unused()
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%def op_unused_e7():
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% unused()
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%def op_unused_e8():
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% unused()
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%def op_unused_e9():
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% unused()
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%def op_unused_ea():
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% unused()
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%def op_unused_eb():
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% unused()
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%def op_unused_ec():
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% unused()
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%def op_unused_ed():
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% unused()
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%def op_unused_ee():
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% unused()
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%def op_unused_ef():
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% unused()
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%def op_unused_f0():
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% unused()
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%def op_unused_f1():
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% unused()
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%def op_unused_f2():
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% unused()
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%def op_unused_f3():
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% unused()
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%def op_unused_f4():
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% unused()
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%def op_unused_f5():
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% unused()
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%def op_unused_f6():
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% unused()
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%def op_unused_f7():
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% unused()
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%def op_unused_f8():
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% unused()
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%def op_unused_f9():
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% unused()
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%def op_unused_fc():
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% unused()
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%def op_unused_fd():
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% unused()
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