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626 lines
18 KiB
626 lines
18 KiB
%def bindiv(result="", second="", tmp="", wide="", suffix="", rem="0", ext="cdq"):
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/*
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* 32-bit binary div/rem operation. Handles special case of op1=-1.
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*/
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/* div/rem vAA, vBB, vCC */
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movzbq 2(rPC), %rax # rax <- BB
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movzbq 3(rPC), %rcx # rcx <- CC
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.if $wide
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GET_WIDE_VREG %rax, %rax # eax <- vBB
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GET_WIDE_VREG $second, %rcx # ecx <- vCC
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.else
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GET_VREG %eax, %rax # eax <- vBB
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GET_VREG $second, %rcx # ecx <- vCC
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.endif
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test${suffix} $second, $second
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jz common_errDivideByZero
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cmp${suffix} $$-1, $second
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je 2f
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cmp${suffix} $$2, $second
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je 3f
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$ext # rdx:rax <- sign-extended of rax
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idiv${suffix} $second
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1:
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.if $wide
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SET_WIDE_VREG $result, rINSTq # eax <- vBB
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.else
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SET_VREG $result, rINSTq # eax <- vBB
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.endif
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
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2:
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.if $rem
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xor${suffix} $result, $result
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.else
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neg${suffix} $result
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.endif
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jmp 1b
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3:
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.if $rem
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mov${suffix} $tmp, $result
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.if $wide
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shr${suffix} $$63, $result
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.else
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shr${suffix} $$31, $result
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.endif
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add${suffix} $tmp, $result
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and${suffix} $$-2, $result
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sub${suffix} $result, $tmp
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mov${suffix} $tmp, $result
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.else
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mov${suffix} $result, $tmp
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.if $wide
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shr${suffix} $$63, $tmp
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.else
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shr${suffix} $$31, $tmp
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.endif
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add${suffix} $tmp, $result
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sar${suffix} $result
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.endif
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jmp 1b
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%def bindiv2addr(result="", second="", tmp="", wide="", suffix="", rem="0", ext="cdq"):
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/*
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* 32-bit binary div/rem operation. Handles special case of op1=-1.
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*/
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/* div/rem/2addr vA, vB */
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movl rINST, %ecx # rcx <- BA
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sarl $$4, %ecx # rcx <- B
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andb $$0xf, rINSTbl # rINST <- A
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.if $wide
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GET_WIDE_VREG %rax, rINSTq # eax <- vA
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GET_WIDE_VREG $second, %rcx # ecx <- vB
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.else
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GET_VREG %eax, rINSTq # eax <- vA
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GET_VREG $second, %rcx # ecx <- vB
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.endif
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test${suffix} $second, $second
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jz common_errDivideByZero
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cmp${suffix} $$-1, $second
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je 2f
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cmp${suffix} $$2, $second
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je 3f
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$ext # rdx:rax <- sign-extended of rax
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idiv${suffix} $second
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1:
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.if $wide
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SET_WIDE_VREG $result, rINSTq # vA <- result
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.else
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SET_VREG $result, rINSTq # vA <- result
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.endif
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
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2:
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.if $rem
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xor${suffix} $result, $result
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.else
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neg${suffix} $result
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.endif
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jmp 1b
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3:
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.if $rem
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mov${suffix} $tmp, $result
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.if $wide
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shr${suffix} $$63, $result
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.else
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shr${suffix} $$31, $result
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.endif
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add${suffix} $tmp, $result
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and${suffix} $$-2, $result
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sub${suffix} $result, $tmp
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mov${suffix} $tmp, $result
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.else
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mov${suffix} $result, $tmp
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.if $wide
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shr${suffix} $$63, $tmp
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.else
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shr${suffix} $$31, $tmp
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.endif
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add${suffix} $tmp, $result
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sar${suffix} $result
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.endif
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jmp 1b
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%def bindivLit16(result="", rem="0"):
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/*
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* 32-bit binary div/rem operation. Handles special case of op1=-1.
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*/
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/* div/rem/lit16 vA, vB, #+CCCC */
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/* Need A in rINST, ssssCCCC in ecx, vB in eax */
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movl rINST, %eax # rax <- 000000BA
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sarl $$4, %eax # eax <- B
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GET_VREG %eax, %rax # eax <- vB
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movswl 2(rPC), %ecx # ecx <- ssssCCCC
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andb $$0xf, rINSTbl # rINST <- A
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testl %ecx, %ecx
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jz common_errDivideByZero
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cmpl $$-1, %ecx
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je 2f
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cdq # rax <- sign-extended of eax
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idivl %ecx
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1:
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SET_VREG $result, rINSTq # vA <- result
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
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2:
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.if $rem
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xorl $result, $result
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.else
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negl $result
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.endif
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jmp 1b
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%def bindivLit8(result="", rem="0"):
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/*
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* 32-bit div/rem "lit8" binary operation. Handles special case of
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* op0=minint & op1=-1
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*/
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/* div/rem/lit8 vAA, vBB, #+CC */
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movzbq 2(rPC), %rax # eax <- BB
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movsbl 3(rPC), %ecx # ecx <- ssssssCC
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GET_VREG %eax, %rax # eax <- rBB
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testl %ecx, %ecx
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je common_errDivideByZero
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cmpl $$-1, %ecx
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je 2f
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cdq # rax <- sign-extended of eax
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idivl %ecx
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1:
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SET_VREG $result, rINSTq # vA <- result
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
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2:
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.if $rem
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xorl $result, $result
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.else
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negl $result
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.endif
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jmp 1b
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%def binop(result="%eax", instr=""):
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/*
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* Generic 32-bit binary operation. Provide an "instr" line that
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* specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
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* This could be an x86 instruction or a function call. (If the result
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* comes back in a register other than eax, you can override "result".)
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*
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* For: add-int, sub-int, and-int, or-int,
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* xor-int, shl-int, shr-int, ushr-int
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*/
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/* binop vAA, vBB, vCC */
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movzbq 2(rPC), %rax # rax <- BB
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movzbq 3(rPC), %rcx # rcx <- CC
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GET_VREG %eax, %rax # eax <- vBB
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$instr VREG_ADDRESS(%rcx),%eax
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SET_VREG $result, rINSTq
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
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%def binop1(wide="0", instr=""):
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/*
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* Generic 32-bit binary operation in which both operands loaded to
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* registers (op0 in eax, op1 in ecx).
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*/
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/* binop vAA, vBB, vCC */
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movzbq 2(rPC), %rax # eax <- BB
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movzbq 3(rPC), %rcx # ecx <- CC
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GET_VREG %ecx, %rcx # eax <- vCC
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.if $wide
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GET_WIDE_VREG %rax, %rax # rax <- vBB
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$instr # ex: addl %ecx,%eax
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SET_WIDE_VREG %rax, rINSTq
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.else
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GET_VREG %eax, %rax # eax <- vBB
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$instr # ex: addl %ecx,%eax
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SET_VREG %eax, rINSTq
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.endif
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
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%def binop2addr(result="%eax", instr=""):
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/*
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* Generic 32-bit "/2addr" binary operation. Provide an "instr" line
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* that specifies an instruction that performs "result = r0 op r1".
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* This could be an instruction or a function call.
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*
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* For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
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* rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
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* shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
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* sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
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*/
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/* binop/2addr vA, vB */
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movl rINST, %ecx # rcx <- A+
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sarl $$4, rINST # rINST <- B
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andb $$0xf, %cl # ecx <- A
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GET_VREG %eax, rINSTq # eax <- vB
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$instr %eax, VREG_ADDRESS(%rcx)
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CLEAR_REF %rcx
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
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%def binopLit16(result="%eax", instr=""):
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/*
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* Generic 32-bit "lit16" binary operation. Provide an "instr" line
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* that specifies an instruction that performs "result = eax op ecx".
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* This could be an x86 instruction or a function call. (If the result
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* comes back in a register other than eax, you can override "result".)
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*
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* For: add-int/lit16, rsub-int,
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* and-int/lit16, or-int/lit16, xor-int/lit16
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*/
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/* binop/lit16 vA, vB, #+CCCC */
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movl rINST, %eax # rax <- 000000BA
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sarl $$4, %eax # eax <- B
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GET_VREG %eax, %rax # eax <- vB
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andb $$0xf, rINSTbl # rINST <- A
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movswl 2(rPC), %ecx # ecx <- ssssCCCC
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$instr # for example: addl %ecx, %eax
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SET_VREG $result, rINSTq
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
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%def binopLit8(result="%eax", instr=""):
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/*
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* Generic 32-bit "lit8" binary operation. Provide an "instr" line
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* that specifies an instruction that performs "result = eax op ecx".
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* This could be an x86 instruction or a function call. (If the result
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* comes back in a register other than r0, you can override "result".)
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*
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* For: add-int/lit8, rsub-int/lit8
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* and-int/lit8, or-int/lit8, xor-int/lit8,
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* shl-int/lit8, shr-int/lit8, ushr-int/lit8
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*/
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/* binop/lit8 vAA, vBB, #+CC */
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movzbq 2(rPC), %rax # rax <- BB
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movsbl 3(rPC), %ecx # rcx <- ssssssCC
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GET_VREG %eax, %rax # eax <- rBB
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$instr # ex: addl %ecx,%eax
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SET_VREG $result, rINSTq
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
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%def binopWide(instr=""):
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/*
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* Generic 64-bit binary operation.
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*/
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/* binop vAA, vBB, vCC */
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movzbq 2(rPC), %rax # eax <- BB
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movzbq 3(rPC), %rcx # ecx <- CC
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GET_WIDE_VREG %rax, %rax # rax <- v[BB]
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$instr VREG_ADDRESS(%rcx),%rax
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SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
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%def binopWide2addr(instr=""):
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/*
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* Generic 64-bit binary operation.
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*/
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/* binop/2addr vA, vB */
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movl rINST, %ecx # rcx <- A+
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sarl $$4, rINST # rINST <- B
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andb $$0xf, %cl # ecx <- A
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GET_WIDE_VREG %rax, rINSTq # rax <- vB
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$instr %rax,VREG_ADDRESS(%rcx)
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CLEAR_WIDE_REF %rcx
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
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%def cvtfp_int(fp_suffix="", i_suffix="", max_const="", result_reg="", wide=""):
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/* On fp to int conversions, Java requires that
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* if the result > maxint, it should be clamped to maxint. If it is less
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* than minint, it should be clamped to minint. If it is a nan, the result
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* should be zero. Further, the rounding mode is to truncate.
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*/
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/* float/double to int/long vA, vB */
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movl rINST, %ecx # rcx <- A+
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sarl $$4, rINST # rINST <- B
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andb $$0xf, %cl # ecx <- A
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GET_VREG_XMM${fp_suffix} %xmm0, rINSTq
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mov${i_suffix} ${max_const}, ${result_reg}
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cvtsi2s${fp_suffix}${i_suffix} ${result_reg}, %xmm1
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comis${fp_suffix} %xmm1, %xmm0
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jae 1f
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jp 2f
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cvtts${fp_suffix}2si${i_suffix} %xmm0, ${result_reg}
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jmp 1f
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2:
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xor${i_suffix} ${result_reg}, ${result_reg}
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1:
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.if $wide
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SET_WIDE_VREG ${result_reg}, %rcx
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.else
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SET_VREG ${result_reg}, %rcx
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.endif
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
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%def shop2addr(wide="0", instr=""):
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/*
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* Generic 32-bit "shift/2addr" operation.
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*/
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/* shift/2addr vA, vB */
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movl rINST, %ecx # ecx <- BA
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sarl $$4, %ecx # ecx <- B
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GET_VREG %ecx, %rcx # ecx <- vBB
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andb $$0xf, rINSTbl # rINST <- A
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.if $wide
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GET_WIDE_VREG %rax, rINSTq # rax <- vAA
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$instr # ex: sarl %cl, %eax
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SET_WIDE_VREG %rax, rINSTq
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.else
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GET_VREG %eax, rINSTq # eax <- vAA
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$instr # ex: sarl %cl, %eax
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SET_VREG %eax, rINSTq
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.endif
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
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%def unop(preinstr="", instr="", wide="0"):
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/*
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* Generic 32/64-bit unary operation. Provide an "instr" line that
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* specifies an instruction that performs "result = op eax".
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*/
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/* unop vA, vB */
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movl rINST, %ecx # rcx <- A+
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sarl $$4,rINST # rINST <- B
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.if ${wide}
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GET_WIDE_VREG %rax, rINSTq # rax <- vB
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.else
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GET_VREG %eax, rINSTq # eax <- vB
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.endif
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andb $$0xf,%cl # ecx <- A
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$preinstr
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$instr
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.if ${wide}
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SET_WIDE_VREG %rax, %rcx
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.else
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SET_VREG %eax, %rcx
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.endif
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
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%def op_add_int():
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% binop(instr="addl")
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%def op_add_int_2addr():
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% binop2addr(instr="addl")
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%def op_add_int_lit16():
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% binopLit16(instr="addl %ecx, %eax")
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%def op_add_int_lit8():
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% binopLit8(instr="addl %ecx, %eax")
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%def op_add_long():
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% binopWide(instr="addq")
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%def op_add_long_2addr():
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% binopWide2addr(instr="addq")
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%def op_and_int():
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% binop(instr="andl")
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%def op_and_int_2addr():
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% binop2addr(instr="andl")
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%def op_and_int_lit16():
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% binopLit16(instr="andl %ecx, %eax")
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%def op_and_int_lit8():
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% binopLit8(instr="andl %ecx, %eax")
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%def op_and_long():
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% binopWide(instr="andq")
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%def op_and_long_2addr():
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% binopWide2addr(instr="andq")
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%def op_cmp_long():
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/*
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* Compare two 64-bit values. Puts 0, 1, or -1 into the destination
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* register based on the results of the comparison.
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*/
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/* cmp-long vAA, vBB, vCC */
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movzbq 2(rPC), %rdx # edx <- BB
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movzbq 3(rPC), %rcx # ecx <- CC
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GET_WIDE_VREG %rdx, %rdx # rdx <- v[BB]
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xorl %eax, %eax
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xorl %edi, %edi
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addb $$1, %al
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movl $$-1, %esi
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cmpq VREG_ADDRESS(%rcx), %rdx
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cmovl %esi, %edi
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cmovg %eax, %edi
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SET_VREG %edi, rINSTq
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
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%def op_div_int():
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% bindiv(result="%eax", second="%ecx", tmp="%edx", wide="0", suffix="l")
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%def op_div_int_2addr():
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% bindiv2addr(result="%eax", second="%ecx", tmp="%edx", wide="0", suffix="l")
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%def op_div_int_lit16():
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% bindivLit16(result="%eax")
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%def op_div_int_lit8():
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% bindivLit8(result="%eax")
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%def op_div_long():
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% bindiv(result="%rax", second="%rcx", tmp="%rdx", wide="1", suffix="q", ext="cqo")
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%def op_div_long_2addr():
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% bindiv2addr(result="%rax", second="%rcx", tmp="%rdx", wide="1", suffix="q", ext="cqo")
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%def op_int_to_byte():
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% unop(instr="movsbl %al, %eax")
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%def op_int_to_char():
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% unop(instr="movzwl %ax,%eax")
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%def op_int_to_long():
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/* int to long vA, vB */
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movzbq rINSTbl, %rax # rax <- +A
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sarl $$4, %eax # eax <- B
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andb $$0xf, rINSTbl # rINST <- A
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movslq VREG_ADDRESS(%rax), %rax
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SET_WIDE_VREG %rax, rINSTq # v[A] <- %rax
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
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%def op_int_to_short():
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% unop(instr="movswl %ax, %eax")
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%def op_long_to_int():
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/* we ignore the high word, making this equivalent to a 32-bit reg move */
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% op_move()
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%def op_mul_int():
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% binop(instr="imull")
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%def op_mul_int_2addr():
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/* mul vA, vB */
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movl rINST, %ecx # rcx <- A+
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sarl $$4, rINST # rINST <- B
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andb $$0xf, %cl # ecx <- A
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GET_VREG %eax, %rcx # eax <- vA
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imull (rFP,rINSTq,4), %eax
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SET_VREG %eax, %rcx
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
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%def op_mul_int_lit16():
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% binopLit16(instr="imull %ecx, %eax")
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%def op_mul_int_lit8():
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% binopLit8(instr="imull %ecx, %eax")
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%def op_mul_long():
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% binopWide(instr="imulq")
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%def op_mul_long_2addr():
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/* mul vA, vB */
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movl rINST, %ecx # rcx <- A+
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sarl $$4, rINST # rINST <- B
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andb $$0xf, %cl # ecx <- A
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GET_WIDE_VREG %rax, %rcx # rax <- vA
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imulq (rFP,rINSTq,4), %rax
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SET_WIDE_VREG %rax, %rcx
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
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%def op_neg_int():
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% unop(instr=" negl %eax")
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%def op_neg_long():
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% unop(instr=" negq %rax", wide="1")
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%def op_not_int():
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% unop(instr=" notl %eax")
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%def op_not_long():
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% unop(instr=" notq %rax", wide="1")
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%def op_or_int():
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% binop(instr="orl")
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%def op_or_int_2addr():
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% binop2addr(instr="orl")
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%def op_or_int_lit16():
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% binopLit16(instr="orl %ecx, %eax")
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%def op_or_int_lit8():
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% binopLit8(instr="orl %ecx, %eax")
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%def op_or_long():
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% binopWide(instr="orq")
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%def op_or_long_2addr():
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% binopWide2addr(instr="orq")
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%def op_rem_int():
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% bindiv(result="%edx", second="%ecx", tmp="%eax", wide="0", suffix="l", rem="1")
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%def op_rem_int_2addr():
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% bindiv2addr(result="%edx", second="%ecx", tmp="%eax", wide="0", suffix="l", rem="1")
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%def op_rem_int_lit16():
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% bindivLit16(result="%edx", rem="1")
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%def op_rem_int_lit8():
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% bindivLit8(result="%edx", rem="1")
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%def op_rem_long():
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% bindiv(result="%rdx", second="%rcx", tmp="%rax", wide="1", suffix="q", ext="cqo", rem="1")
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%def op_rem_long_2addr():
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% bindiv2addr(result="%rdx", second="%rcx", tmp="%rax", wide="1", suffix="q", rem="1", ext="cqo")
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%def op_rsub_int():
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/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */
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% binopLit16(instr="subl %eax, %ecx", result="%ecx")
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%def op_rsub_int_lit8():
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% binopLit8(instr="subl %eax, %ecx", result="%ecx")
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%def op_shl_int():
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% binop1(instr="sall %cl, %eax")
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%def op_shl_int_2addr():
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% shop2addr(instr="sall %cl, %eax")
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%def op_shl_int_lit8():
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% binopLit8(instr="sall %cl, %eax")
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%def op_shl_long():
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% binop1(instr="salq %cl, %rax", wide="1")
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%def op_shl_long_2addr():
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% shop2addr(instr="salq %cl, %rax", wide="1")
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%def op_shr_int():
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% binop1(instr="sarl %cl, %eax")
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%def op_shr_int_2addr():
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% shop2addr(instr="sarl %cl, %eax")
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%def op_shr_int_lit8():
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% binopLit8(instr="sarl %cl, %eax")
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%def op_shr_long():
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% binop1(instr="sarq %cl, %rax", wide="1")
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%def op_shr_long_2addr():
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% shop2addr(instr="sarq %cl, %rax", wide="1")
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%def op_sub_int():
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% binop(instr="subl")
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%def op_sub_int_2addr():
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% binop2addr(instr="subl")
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%def op_sub_long():
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% binopWide(instr="subq")
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%def op_sub_long_2addr():
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% binopWide2addr(instr="subq")
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%def op_ushr_int():
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% binop1(instr="shrl %cl, %eax")
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%def op_ushr_int_2addr():
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% shop2addr(instr="shrl %cl, %eax")
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%def op_ushr_int_lit8():
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% binopLit8(instr="shrl %cl, %eax")
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%def op_ushr_long():
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% binop1(instr="shrq %cl, %rax", wide="1")
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%def op_ushr_long_2addr():
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% shop2addr(instr="shrq %cl, %rax", wide="1")
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%def op_xor_int():
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% binop(instr="xorl")
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%def op_xor_int_2addr():
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% binop2addr(instr="xorl")
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%def op_xor_int_lit16():
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% binopLit16(instr="xorl %ecx, %eax")
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%def op_xor_int_lit8():
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% binopLit8(instr="xorl %ecx, %eax")
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%def op_xor_long():
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% binopWide(instr="xorq")
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%def op_xor_long_2addr():
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% binopWide2addr(instr="xorq")
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