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196 lines
5.9 KiB
196 lines
5.9 KiB
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _SDE_DRM_H_
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#define _SDE_DRM_H_
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#include "drm.h"
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#define SDE_MAX_PLANES 4
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#define SDE_MAX_DE_CURVES 3
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#define FILTER_EDGE_DIRECTED_2D 0x0
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#define FILTER_CIRCULAR_2D 0x1
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#define FILTER_SEPARABLE_1D 0x2
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#define FILTER_BILINEAR 0x3
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#define FILTER_ALPHA_DROP_REPEAT 0x0
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#define FILTER_ALPHA_BILINEAR 0x1
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#define FILTER_ALPHA_2D 0x3
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#define FILTER_BLEND_CIRCULAR_2D 0x0
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#define FILTER_BLEND_SEPARABLE_1D 0x1
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#define SCALER_LUT_SWAP 0x1
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#define SCALER_LUT_DIR_WR 0x2
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#define SCALER_LUT_Y_CIR_WR 0x4
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#define SCALER_LUT_UV_CIR_WR 0x8
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#define SCALER_LUT_Y_SEP_WR 0x10
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#define SCALER_LUT_UV_SEP_WR 0x20
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#define SDE_DRM_BLEND_OP_NOT_DEFINED 0
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#define SDE_DRM_BLEND_OP_OPAQUE 1
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#define SDE_DRM_BLEND_OP_PREMULTIPLIED 2
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#define SDE_DRM_BLEND_OP_COVERAGE 3
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#define SDE_DRM_BLEND_OP_MAX 4
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#define SDE_DRM_DEINTERLACE 0
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#define SDE_DRM_BITMASK_COUNT 64
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#define SDE_DRM_FB_NON_SEC 0
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#define SDE_DRM_FB_SEC 1
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#define SDE_DRM_FB_NON_SEC_DIR_TRANS 2
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#define SDE_DRM_FB_SEC_DIR_TRANS 3
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#define SDE_DRM_SEC_NON_SEC 0
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#define SDE_DRM_SEC_ONLY 1
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struct sde_drm_pix_ext_v1 {
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int32_t num_ext_pxls_lr[SDE_MAX_PLANES];
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int32_t num_ext_pxls_tb[SDE_MAX_PLANES];
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int32_t left_ftch[SDE_MAX_PLANES];
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int32_t right_ftch[SDE_MAX_PLANES];
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int32_t top_ftch[SDE_MAX_PLANES];
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int32_t btm_ftch[SDE_MAX_PLANES];
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int32_t left_rpt[SDE_MAX_PLANES];
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int32_t right_rpt[SDE_MAX_PLANES];
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int32_t top_rpt[SDE_MAX_PLANES];
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int32_t btm_rpt[SDE_MAX_PLANES];
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};
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struct sde_drm_scaler_v1 {
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struct sde_drm_pix_ext_v1 pe;
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int32_t init_phase_x[SDE_MAX_PLANES];
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int32_t phase_step_x[SDE_MAX_PLANES];
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int32_t init_phase_y[SDE_MAX_PLANES];
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int32_t phase_step_y[SDE_MAX_PLANES];
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uint32_t horz_filter[SDE_MAX_PLANES];
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uint32_t vert_filter[SDE_MAX_PLANES];
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};
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struct sde_drm_de_v1 {
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uint32_t enable;
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int16_t sharpen_level1;
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int16_t sharpen_level2;
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uint16_t clip;
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uint16_t limit;
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uint16_t thr_quiet;
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uint16_t thr_dieout;
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uint16_t thr_low;
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uint16_t thr_high;
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uint16_t prec_shift;
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int16_t adjust_a[SDE_MAX_DE_CURVES];
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int16_t adjust_b[SDE_MAX_DE_CURVES];
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int16_t adjust_c[SDE_MAX_DE_CURVES];
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};
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#define SDE_DYN_EXP_DISABLE 0x1
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#define SDE_DRM_QSEED3LITE
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#define SDE_DRM_QSEED4
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#define SDE_DRM_INLINE_PREDOWNSCALE
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struct sde_drm_scaler_v2 {
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uint32_t enable;
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uint32_t dir_en;
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struct sde_drm_pix_ext_v1 pe;
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uint32_t horz_decimate;
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uint32_t vert_decimate;
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int32_t init_phase_x[SDE_MAX_PLANES];
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int32_t phase_step_x[SDE_MAX_PLANES];
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int32_t init_phase_y[SDE_MAX_PLANES];
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int32_t phase_step_y[SDE_MAX_PLANES];
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uint32_t preload_x[SDE_MAX_PLANES];
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uint32_t preload_y[SDE_MAX_PLANES];
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uint32_t src_width[SDE_MAX_PLANES];
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uint32_t src_height[SDE_MAX_PLANES];
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uint32_t dst_width;
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uint32_t dst_height;
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uint32_t y_rgb_filter_cfg;
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uint32_t uv_filter_cfg;
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uint32_t alpha_filter_cfg;
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uint32_t blend_cfg;
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uint32_t lut_flag;
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uint32_t dir_lut_idx;
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uint32_t y_rgb_cir_lut_idx;
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uint32_t uv_cir_lut_idx;
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uint32_t y_rgb_sep_lut_idx;
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uint32_t uv_sep_lut_idx;
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struct sde_drm_de_v1 de;
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uint32_t dir_weight;
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uint32_t unsharp_mask_blend;
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uint32_t de_blend;
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uint32_t flags;
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uint32_t pre_downscale_x_0;
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uint32_t pre_downscale_x_1;
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uint32_t pre_downscale_y_0;
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uint32_t pre_downscale_y_1;
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};
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#define SDE_MAX_DS_COUNT 2
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#define SDE_DRM_DESTSCALER_ENABLE 0x1
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#define SDE_DRM_DESTSCALER_SCALE_UPDATE 0x2
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#define SDE_DRM_DESTSCALER_ENHANCER_UPDATE 0x4
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#define SDE_DRM_DESTSCALER_PU_ENABLE 0x8
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struct sde_drm_dest_scaler_cfg {
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uint32_t flags;
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uint32_t index;
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uint32_t lm_width;
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uint32_t lm_height;
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uint64_t scaler_cfg;
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};
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struct sde_drm_dest_scaler_data {
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uint32_t num_dest_scaler;
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struct sde_drm_dest_scaler_cfg ds_cfg[SDE_MAX_DS_COUNT];
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};
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#define SDE_CSC_MATRIX_COEFF_SIZE 9
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#define SDE_CSC_CLAMP_SIZE 6
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#define SDE_CSC_BIAS_SIZE 3
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struct sde_drm_csc_v1 {
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int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE];
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uint32_t pre_bias[SDE_CSC_BIAS_SIZE];
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uint32_t post_bias[SDE_CSC_BIAS_SIZE];
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uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE];
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uint32_t post_clamp[SDE_CSC_CLAMP_SIZE];
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};
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struct sde_drm_color {
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uint32_t color_0;
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uint32_t color_1;
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uint32_t color_2;
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uint32_t color_3;
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};
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#define SDE_MAX_DIM_LAYERS 7
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#define SDE_DRM_DIM_LAYER_INCLUSIVE 0x1
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#define SDE_DRM_DIM_LAYER_EXCLUSIVE 0x2
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struct sde_drm_dim_layer_cfg {
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uint32_t flags;
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uint32_t stage;
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struct sde_drm_color color_fill;
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struct drm_clip_rect rect;
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};
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struct sde_drm_dim_layer_v1 {
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uint32_t num_layers;
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struct sde_drm_dim_layer_cfg layer_cfg[SDE_MAX_DIM_LAYERS];
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};
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#define SDE_DRM_WB_CFG 0x1
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#define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1 << 0)
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struct sde_drm_wb_cfg {
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uint32_t flags;
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uint32_t connector_id;
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uint32_t count_modes;
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uint64_t modes;
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};
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#define SDE_MAX_ROI_V1 4
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struct sde_drm_roi_v1 {
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uint32_t num_rects;
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struct drm_clip_rect roi[SDE_MAX_ROI_V1];
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};
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#define SDE_MODE_DPMS_ON 0
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#define SDE_MODE_DPMS_LP1 1
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#define SDE_MODE_DPMS_LP2 2
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#define SDE_MODE_DPMS_STANDBY 3
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#define SDE_MODE_DPMS_SUSPEND 4
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#define SDE_MODE_DPMS_OFF 5
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#define SDE_RECOVERY_SUCCESS 0
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#define SDE_RECOVERY_CAPTURE 1
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#define SDE_RECOVERY_HARD_RESET 2
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#endif
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