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185 lines
6.3 KiB
185 lines
6.3 KiB
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _H_MSM_VPU_H_
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#define _H_MSM_VPU_H_
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#include <linux/videodev2.h>
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#define V4L2_BUF_FLAG_CDS_ENABLE 0x10000000
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#define V4L2_PLANE_MEM_OFFSET 0
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enum vpu_colorspace {
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VPU_CS_MIN = 0,
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VPU_CS_RGB_FULL = 1,
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VPU_CS_RGB_LIMITED = 2,
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VPU_CS_REC601_FULL = 3,
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VPU_CS_REC601_LIMITED = 4,
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VPU_CS_REC709_FULL = 5,
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VPU_CS_REC709_LIMITED = 6,
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VPU_CS_SMPTE240_FULL = 7,
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VPU_CS_SMPTE240_LIMITED = 8,
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VPU_CS_MAX = 9,
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};
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#define VPU_FMT_EXT_FLAG_BT 1
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#define VPU_FMT_EXT_FLAG_TB 2
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#define VPU_FMT_EXT_FLAG_3D 4
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struct v4l2_format_vpu_extension {
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__u8 flag;
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__u8 gap_in_lines;
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};
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#define V4L2_PIX_FMT_XRGB2 v4l2_fourcc('X', 'R', 'G', '2')
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#define V4L2_PIX_FMT_XBGR2 v4l2_fourcc('X', 'B', 'G', '2')
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#define V4L2_PIX_FMT_YUYV10 v4l2_fourcc('Y', 'U', 'Y', 'L')
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#define V4L2_PIX_FMT_YUV8 v4l2_fourcc('Y', 'U', 'V', '8')
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#define V4L2_PIX_FMT_YUV10 v4l2_fourcc('Y', 'U', 'V', 'L')
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#define V4L2_PIX_FMT_YUYV10BWC v4l2_fourcc('Y', 'B', 'W', 'C')
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#define VPU_INPUT_TYPE_HOST 0
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#define VPU_INPUT_TYPE_VCAP 1
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#define VPU_OUTPUT_TYPE_HOST 0
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#define VPU_OUTPUT_TYPE_DISPLAY 1
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#define VPU_PIPE_VCAP0 (1 << 16)
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#define VPU_PIPE_VCAP1 (1 << 17)
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#define VPU_PIPE_DISPLAY0 (1 << 18)
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#define VPU_PIPE_DISPLAY1 (1 << 19)
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#define VPU_PIPE_DISPLAY2 (1 << 20)
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#define VPU_PIPE_DISPLAY3 (1 << 21)
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#define VPU_PRIVATE_EVENT_BASE (V4L2_EVENT_PRIVATE_START + 6 * 1000)
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enum VPU_PRIVATE_EVENT {
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VPU_EVENT_START = VPU_PRIVATE_EVENT_BASE,
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VPU_EVENT_FLUSH_DONE = VPU_EVENT_START + 1,
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VPU_EVENT_ACTIVE_REGION_CHANGED = VPU_EVENT_START + 2,
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VPU_EVENT_SESSION_TIMESTAMP = VPU_EVENT_START + 3,
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VPU_EVENT_SESSION_CREATED = VPU_EVENT_START + 4,
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VPU_EVENT_SESSION_FREED = VPU_EVENT_START + 5,
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VPU_EVENT_SESSION_CLIENT_EXITED = VPU_EVENT_START + 6,
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VPU_EVENT_HW_ERROR = VPU_EVENT_START + 11,
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VPU_EVENT_INVALID_CONFIG = VPU_EVENT_START + 12,
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VPU_EVENT_FAILED_SESSION_STREAMING = VPU_EVENT_START + 13,
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VPU_EVENT_END
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};
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struct vpu_ctrl_standard {
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__u32 enable;
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__s32 value;
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};
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struct vpu_ctrl_auto_manual {
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__u32 enable;
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__u32 auto_mode;
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__s32 value;
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};
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struct vpu_ctrl_range_mapping {
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__u32 enable;
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__u32 y_range;
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__u32 uv_range;
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};
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#define VPU_ACTIVE_REGION_N_EXCLUSIONS 1
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struct vpu_ctrl_active_region_param {
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__u32 enable;
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__u32 num_exclusions;
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struct v4l2_rect detection_region;
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struct v4l2_rect excluded_regions[VPU_ACTIVE_REGION_N_EXCLUSIONS];
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};
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struct vpu_ctrl_deinterlacing_mode {
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__u32 field_polarity;
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__u32 mvp_mode;
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};
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struct vpu_ctrl_hqv {
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__u32 enable;
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__u32 sharpen_strength;
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__u32 auto_nr_strength;
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};
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struct vpu_info_frame_timestamp {
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__u32 pts_low;
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__u32 pts_high;
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__u32 qtime_low;
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__u32 qtime_high;
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};
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struct vpu_control {
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__u32 control_id;
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union control_data {
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__s32 value;
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struct vpu_ctrl_standard standard;
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struct vpu_ctrl_auto_manual auto_manual;
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struct vpu_ctrl_range_mapping range_mapping;
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struct vpu_ctrl_active_region_param active_region_param;
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struct v4l2_rect active_region_result;
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struct vpu_ctrl_deinterlacing_mode deinterlacing_mode;
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struct vpu_ctrl_hqv hqv;
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struct vpu_info_frame_timestamp timestamp;
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__u8 reserved[124];
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} data;
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};
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#define VPU_CTRL_ID_MIN 0
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#define VPU_CTRL_NOISE_REDUCTION 1
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#define VPU_CTRL_IMAGE_ENHANCEMENT 2
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#define VPU_CTRL_ANAMORPHIC_SCALING 3
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#define VPU_CTRL_DIRECTIONAL_INTERPOLATION 4
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#define VPU_CTRL_BACKGROUND_COLOR 5
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#define VPU_CTRL_RANGE_MAPPING 6
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#define VPU_CTRL_DEINTERLACING_MODE 7
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#define VPU_CTRL_ACTIVE_REGION_PARAM 8
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#define VPU_CTRL_ACTIVE_REGION_RESULT 9
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#define VPU_CTRL_PRIORITY 10
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#define VPU_CTRL_CONTENT_PROTECTION 11
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#define VPU_CTRL_DISPLAY_REFRESH_RATE 12
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#define VPU_CTRL_HQV 20
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#define VPU_CTRL_HQV_SHARPEN 21
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#define VPU_CTRL_HQV_AUTONR 22
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#define VPU_CTRL_ACE 23
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#define VPU_CTRL_ACE_BRIGHTNESS 24
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#define VPU_CTRL_ACE_CONTRAST 25
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#define VPU_CTRL_2D3D 26
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#define VPU_CTRL_2D3D_DEPTH 27
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#define VPU_CTRL_FRC 28
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#define VPU_CTRL_FRC_MOTION_SMOOTHNESS 29
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#define VPU_CTRL_FRC_MOTION_CLEAR 30
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#define VPU_INFO_TIMESTAMP 35
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#define VPU_CTRL_TIMESTAMP_INFO_MODE 36
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#define VPU_INFO_STATISTICS 37
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#define VPU_CTRL_LATENCY 38
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#define VPU_CTRL_LATENCY_MODE 39
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#define VPU_CTRL_ID_MAX 40
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#define VPU_MAX_EXT_DATA_SIZE 720
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struct vpu_control_extended {
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__u32 type;
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__u32 data_len;
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void * data_ptr;
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__u32 buf_size;
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void * buf_ptr;
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};
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struct vpu_control_port {
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__u32 control_id;
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__u32 port;
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union control_port_data {
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__u32 framerate;
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} data;
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};
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#define VPU_CTRL_FPS 1000
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#define VPU_ATTACH_TO_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 1), int)
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#define VPU_QUERY_SESSIONS _IOR('V', (BASE_VIDIOC_PRIVATE + 0), int)
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#define VPU_CREATE_SESSION _IOR('V', (BASE_VIDIOC_PRIVATE + 2), int)
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#define VPU_JOIN_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 3), int)
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#define VPU_CREATE_OUTPUT2 _IO('V', (BASE_VIDIOC_PRIVATE + 5))
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#define VPU_COMMIT_CONFIGURATION _IO('V', (BASE_VIDIOC_PRIVATE + 10))
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#define VPU_FLUSH_BUFS _IOW('V', (BASE_VIDIOC_PRIVATE + 15), enum v4l2_buf_type)
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#define VPU_G_CONTROL _IOWR('V', (BASE_VIDIOC_PRIVATE + 20), struct vpu_control)
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#define VPU_S_CONTROL _IOW('V', (BASE_VIDIOC_PRIVATE + 21), struct vpu_control)
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#define VPU_G_CONTROL_EXTENDED _IOWR('V', (BASE_VIDIOC_PRIVATE + 22), struct vpu_control_extended)
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#define VPU_S_CONTROL_EXTENDED _IOW('V', (BASE_VIDIOC_PRIVATE + 23), struct vpu_control_extended)
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#define VPU_G_CONTROL_PORT _IOWR('V', (BASE_VIDIOC_PRIVATE + 24), struct vpu_control_port)
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#define VPU_S_CONTROL_PORT _IOW('V', (BASE_VIDIOC_PRIVATE + 25), struct vpu_control_port)
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#endif
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