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452 lines
22 KiB
452 lines
22 KiB
#pragma once
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#ifndef FP16_FP16_H
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#define FP16_FP16_H
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#if defined(__cplusplus) && (__cplusplus >= 201103L)
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#include <cstdint>
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#include <cmath>
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#elif !defined(__OPENCL_VERSION__)
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#include <stdint.h>
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#include <math.h>
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#endif
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#ifdef _MSC_VER
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#include <intrin.h>
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#endif
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#include <fp16/bitcasts.h>
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/*
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* Convert a 16-bit floating-point number in IEEE half-precision format, in bit representation, to
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* a 32-bit floating-point number in IEEE single-precision format, in bit representation.
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*
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* @note The implementation doesn't use any floating-point operations.
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*/
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static inline uint32_t fp16_ieee_to_fp32_bits(uint16_t h) {
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/*
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* Extend the half-precision floating-point number to 32 bits and shift to the upper part of the 32-bit word:
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* +---+-----+------------+-------------------+
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* | S |EEEEE|MM MMMM MMMM|0000 0000 0000 0000|
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* +---+-----+------------+-------------------+
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* Bits 31 26-30 16-25 0-15
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*
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* S - sign bit, E - bits of the biased exponent, M - bits of the mantissa, 0 - zero bits.
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*/
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const uint32_t w = (uint32_t) h << 16;
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/*
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* Extract the sign of the input number into the high bit of the 32-bit word:
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*
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* +---+----------------------------------+
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* | S |0000000 00000000 00000000 00000000|
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* +---+----------------------------------+
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* Bits 31 0-31
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*/
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const uint32_t sign = w & UINT32_C(0x80000000);
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/*
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* Extract mantissa and biased exponent of the input number into the bits 0-30 of the 32-bit word:
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*
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* +---+-----+------------+-------------------+
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* | 0 |EEEEE|MM MMMM MMMM|0000 0000 0000 0000|
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* +---+-----+------------+-------------------+
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* Bits 30 27-31 17-26 0-16
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*/
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const uint32_t nonsign = w & UINT32_C(0x7FFFFFFF);
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/*
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* Renorm shift is the number of bits to shift mantissa left to make the half-precision number normalized.
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* If the initial number is normalized, some of its high 6 bits (sign == 0 and 5-bit exponent) equals one.
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* In this case renorm_shift == 0. If the number is denormalize, renorm_shift > 0. Note that if we shift
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* denormalized nonsign by renorm_shift, the unit bit of mantissa will shift into exponent, turning the
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* biased exponent into 1, and making mantissa normalized (i.e. without leading 1).
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*/
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#ifdef _MSC_VER
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unsigned long nonsign_bsr;
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_BitScanReverse(&nonsign_bsr, (unsigned long) nonsign);
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uint32_t renorm_shift = (uint32_t) nonsign_bsr ^ 31;
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#else
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uint32_t renorm_shift = nonsign ? __builtin_clz(nonsign) : 32;
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#endif
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renorm_shift = renorm_shift > 5 ? renorm_shift - 5 : 0;
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/*
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* Iff half-precision number has exponent of 15, the addition overflows it into bit 31,
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* and the subsequent shift turns the high 9 bits into 1. Thus
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* inf_nan_mask ==
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* 0x7F800000 if the half-precision number had exponent of 15 (i.e. was NaN or infinity)
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* 0x00000000 otherwise
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*/
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const int32_t inf_nan_mask = ((int32_t) (nonsign + 0x04000000) >> 8) & INT32_C(0x7F800000);
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/*
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* Iff nonsign is 0, it overflows into 0xFFFFFFFF, turning bit 31 into 1. Otherwise, bit 31 remains 0.
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* The signed shift right by 31 broadcasts bit 31 into all bits of the zero_mask. Thus
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* zero_mask ==
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* 0xFFFFFFFF if the half-precision number was zero (+0.0h or -0.0h)
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* 0x00000000 otherwise
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*/
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const int32_t zero_mask = (int32_t) (nonsign - 1) >> 31;
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/*
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* 1. Shift nonsign left by renorm_shift to normalize it (if the input was denormal)
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* 2. Shift nonsign right by 3 so the exponent (5 bits originally) becomes an 8-bit field and 10-bit mantissa
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* shifts into the 10 high bits of the 23-bit mantissa of IEEE single-precision number.
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* 3. Add 0x70 to the exponent (starting at bit 23) to compensate the different in exponent bias
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* (0x7F for single-precision number less 0xF for half-precision number).
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* 4. Subtract renorm_shift from the exponent (starting at bit 23) to account for renormalization. As renorm_shift
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* is less than 0x70, this can be combined with step 3.
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* 5. Binary OR with inf_nan_mask to turn the exponent into 0xFF if the input was NaN or infinity.
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* 6. Binary ANDNOT with zero_mask to turn the mantissa and exponent into zero if the input was zero.
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* 7. Combine with the sign of the input number.
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*/
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return sign | ((((nonsign << renorm_shift >> 3) + ((0x70 - renorm_shift) << 23)) | inf_nan_mask) & ~zero_mask);
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}
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/*
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* Convert a 16-bit floating-point number in IEEE half-precision format, in bit representation, to
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* a 32-bit floating-point number in IEEE single-precision format.
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*
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* @note The implementation relies on IEEE-like (no assumption about rounding mode and no operations on denormals)
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* floating-point operations and bitcasts between integer and floating-point variables.
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*/
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static inline float fp16_ieee_to_fp32_value(uint16_t h) {
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/*
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* Extend the half-precision floating-point number to 32 bits and shift to the upper part of the 32-bit word:
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* +---+-----+------------+-------------------+
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* | S |EEEEE|MM MMMM MMMM|0000 0000 0000 0000|
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* +---+-----+------------+-------------------+
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* Bits 31 26-30 16-25 0-15
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*
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* S - sign bit, E - bits of the biased exponent, M - bits of the mantissa, 0 - zero bits.
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*/
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const uint32_t w = (uint32_t) h << 16;
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/*
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* Extract the sign of the input number into the high bit of the 32-bit word:
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*
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* +---+----------------------------------+
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* | S |0000000 00000000 00000000 00000000|
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* +---+----------------------------------+
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* Bits 31 0-31
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*/
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const uint32_t sign = w & UINT32_C(0x80000000);
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/*
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* Extract mantissa and biased exponent of the input number into the high bits of the 32-bit word:
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*
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* +-----+------------+---------------------+
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* |EEEEE|MM MMMM MMMM|0 0000 0000 0000 0000|
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* +-----+------------+---------------------+
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* Bits 27-31 17-26 0-16
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*/
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const uint32_t two_w = w + w;
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/*
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* Shift mantissa and exponent into bits 23-28 and bits 13-22 so they become mantissa and exponent
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* of a single-precision floating-point number:
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*
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* S|Exponent | Mantissa
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* +-+---+-----+------------+----------------+
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* |0|000|EEEEE|MM MMMM MMMM|0 0000 0000 0000|
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* +-+---+-----+------------+----------------+
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* Bits | 23-31 | 0-22
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*
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* Next, there are some adjustments to the exponent:
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* - The exponent needs to be corrected by the difference in exponent bias between single-precision and half-precision
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* formats (0x7F - 0xF = 0x70)
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* - Inf and NaN values in the inputs should become Inf and NaN values after conversion to the single-precision number.
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* Therefore, if the biased exponent of the half-precision input was 0x1F (max possible value), the biased exponent
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* of the single-precision output must be 0xFF (max possible value). We do this correction in two steps:
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* - First, we adjust the exponent by (0xFF - 0x1F) = 0xE0 (see exp_offset below) rather than by 0x70 suggested
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* by the difference in the exponent bias (see above).
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* - Then we multiply the single-precision result of exponent adjustment by 2**(-112) to reverse the effect of
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* exponent adjustment by 0xE0 less the necessary exponent adjustment by 0x70 due to difference in exponent bias.
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* The floating-point multiplication hardware would ensure than Inf and NaN would retain their value on at least
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* partially IEEE754-compliant implementations.
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*
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* Note that the above operations do not handle denormal inputs (where biased exponent == 0). However, they also do not
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* operate on denormal inputs, and do not produce denormal results.
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*/
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const uint32_t exp_offset = UINT32_C(0xE0) << 23;
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#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || defined(__GNUC__) && !defined(__STRICT_ANSI__)
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const float exp_scale = 0x1.0p-112f;
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#else
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const float exp_scale = fp32_from_bits(UINT32_C(0x7800000));
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#endif
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const float normalized_value = fp32_from_bits((two_w >> 4) + exp_offset) * exp_scale;
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/*
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* Convert denormalized half-precision inputs into single-precision results (always normalized).
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* Zero inputs are also handled here.
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*
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* In a denormalized number the biased exponent is zero, and mantissa has on-zero bits.
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* First, we shift mantissa into bits 0-9 of the 32-bit word.
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*
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* zeros | mantissa
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* +---------------------------+------------+
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* |0000 0000 0000 0000 0000 00|MM MMMM MMMM|
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* +---------------------------+------------+
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* Bits 10-31 0-9
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*
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* Now, remember that denormalized half-precision numbers are represented as:
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* FP16 = mantissa * 2**(-24).
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* The trick is to construct a normalized single-precision number with the same mantissa and thehalf-precision input
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* and with an exponent which would scale the corresponding mantissa bits to 2**(-24).
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* A normalized single-precision floating-point number is represented as:
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* FP32 = (1 + mantissa * 2**(-23)) * 2**(exponent - 127)
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* Therefore, when the biased exponent is 126, a unit change in the mantissa of the input denormalized half-precision
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* number causes a change of the constructud single-precision number by 2**(-24), i.e. the same ammount.
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*
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* The last step is to adjust the bias of the constructed single-precision number. When the input half-precision number
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* is zero, the constructed single-precision number has the value of
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* FP32 = 1 * 2**(126 - 127) = 2**(-1) = 0.5
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* Therefore, we need to subtract 0.5 from the constructed single-precision number to get the numerical equivalent of
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* the input half-precision number.
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*/
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const uint32_t magic_mask = UINT32_C(126) << 23;
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const float magic_bias = 0.5f;
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const float denormalized_value = fp32_from_bits((two_w >> 17) | magic_mask) - magic_bias;
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/*
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* - Choose either results of conversion of input as a normalized number, or as a denormalized number, depending on the
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* input exponent. The variable two_w contains input exponent in bits 27-31, therefore if its smaller than 2**27, the
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* input is either a denormal number, or zero.
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* - Combine the result of conversion of exponent and mantissa with the sign of the input number.
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*/
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const uint32_t denormalized_cutoff = UINT32_C(1) << 27;
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const uint32_t result = sign |
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(two_w < denormalized_cutoff ? fp32_to_bits(denormalized_value) : fp32_to_bits(normalized_value));
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return fp32_from_bits(result);
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}
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/*
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* Convert a 32-bit floating-point number in IEEE single-precision format to a 16-bit floating-point number in
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* IEEE half-precision format, in bit representation.
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*
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* @note The implementation relies on IEEE-like (no assumption about rounding mode and no operations on denormals)
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* floating-point operations and bitcasts between integer and floating-point variables.
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*/
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static inline uint16_t fp16_ieee_from_fp32_value(float f) {
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#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) || defined(__GNUC__) && !defined(__STRICT_ANSI__)
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const float scale_to_inf = 0x1.0p+112f;
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const float scale_to_zero = 0x1.0p-110f;
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#else
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const float scale_to_inf = fp32_from_bits(UINT32_C(0x77800000));
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const float scale_to_zero = fp32_from_bits(UINT32_C(0x08800000));
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#endif
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float base = (fabsf(f) * scale_to_inf) * scale_to_zero;
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const uint32_t w = fp32_to_bits(f);
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const uint32_t shl1_w = w + w;
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const uint32_t sign = w & UINT32_C(0x80000000);
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uint32_t bias = shl1_w & UINT32_C(0xFF000000);
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if (bias < UINT32_C(0x71000000)) {
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bias = UINT32_C(0x71000000);
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}
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base = fp32_from_bits((bias >> 1) + UINT32_C(0x07800000)) + base;
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const uint32_t bits = fp32_to_bits(base);
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const uint32_t exp_bits = (bits >> 13) & UINT32_C(0x00007C00);
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const uint32_t mantissa_bits = bits & UINT32_C(0x00000FFF);
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const uint32_t nonsign = exp_bits + mantissa_bits;
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return (sign >> 16) | (shl1_w > UINT32_C(0xFF000000) ? UINT16_C(0x7E00) : nonsign);
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}
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/*
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* Convert a 16-bit floating-point number in ARM alternative half-precision format, in bit representation, to
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* a 32-bit floating-point number in IEEE single-precision format, in bit representation.
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*
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* @note The implementation doesn't use any floating-point operations.
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*/
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static inline uint32_t fp16_alt_to_fp32_bits(uint16_t h) {
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/*
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* Extend the half-precision floating-point number to 32 bits and shift to the upper part of the 32-bit word:
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* +---+-----+------------+-------------------+
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* | S |EEEEE|MM MMMM MMMM|0000 0000 0000 0000|
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* +---+-----+------------+-------------------+
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* Bits 31 26-30 16-25 0-15
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*
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* S - sign bit, E - bits of the biased exponent, M - bits of the mantissa, 0 - zero bits.
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*/
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const uint32_t w = (uint32_t) h << 16;
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/*
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* Extract the sign of the input number into the high bit of the 32-bit word:
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*
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* +---+----------------------------------+
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* | S |0000000 00000000 00000000 00000000|
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* +---+----------------------------------+
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* Bits 31 0-31
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*/
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const uint32_t sign = w & UINT32_C(0x80000000);
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/*
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* Extract mantissa and biased exponent of the input number into the bits 0-30 of the 32-bit word:
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*
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* +---+-----+------------+-------------------+
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* | 0 |EEEEE|MM MMMM MMMM|0000 0000 0000 0000|
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* +---+-----+------------+-------------------+
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* Bits 30 27-31 17-26 0-16
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*/
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const uint32_t nonsign = w & UINT32_C(0x7FFFFFFF);
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/*
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* Renorm shift is the number of bits to shift mantissa left to make the half-precision number normalized.
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* If the initial number is normalized, some of its high 6 bits (sign == 0 and 5-bit exponent) equals one.
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* In this case renorm_shift == 0. If the number is denormalize, renorm_shift > 0. Note that if we shift
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* denormalized nonsign by renorm_shift, the unit bit of mantissa will shift into exponent, turning the
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* biased exponent into 1, and making mantissa normalized (i.e. without leading 1).
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*/
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#ifdef _MSC_VER
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unsigned long nonsign_bsr;
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_BitScanReverse(&nonsign_bsr, (unsigned long) nonsign);
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uint32_t renorm_shift = (uint32_t) nonsign_bsr ^ 31;
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#else
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uint32_t renorm_shift = nonsign ? __builtin_clz(nonsign) : 32;
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#endif
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renorm_shift = renorm_shift > 5 ? renorm_shift - 5 : 0;
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/*
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* Iff nonsign is 0, it overflows into 0xFFFFFFFF, turning bit 31 into 1. Otherwise, bit 31 remains 0.
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* The signed shift right by 31 broadcasts bit 31 into all bits of the zero_mask. Thus
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* zero_mask ==
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* 0xFFFFFFFF if the half-precision number was zero (+0.0h or -0.0h)
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* 0x00000000 otherwise
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*/
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const int32_t zero_mask = (int32_t) (nonsign - 1) >> 31;
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/*
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* 1. Shift nonsign left by renorm_shift to normalize it (if the input was denormal)
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* 2. Shift nonsign right by 3 so the exponent (5 bits originally) becomes an 8-bit field and 10-bit mantissa
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* shifts into the 10 high bits of the 23-bit mantissa of IEEE single-precision number.
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* 3. Add 0x70 to the exponent (starting at bit 23) to compensate the different in exponent bias
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* (0x7F for single-precision number less 0xF for half-precision number).
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* 4. Subtract renorm_shift from the exponent (starting at bit 23) to account for renormalization. As renorm_shift
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* is less than 0x70, this can be combined with step 3.
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* 5. Binary ANDNOT with zero_mask to turn the mantissa and exponent into zero if the input was zero.
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* 6. Combine with the sign of the input number.
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*/
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return sign | (((nonsign << renorm_shift >> 3) + ((0x70 - renorm_shift) << 23)) & ~zero_mask);
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}
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/*
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* Convert a 16-bit floating-point number in ARM alternative half-precision format, in bit representation, to
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* a 32-bit floating-point number in IEEE single-precision format.
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*
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* @note The implementation relies on IEEE-like (no assumption about rounding mode and no operations on denormals)
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* floating-point operations and bitcasts between integer and floating-point variables.
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*/
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static inline float fp16_alt_to_fp32_value(uint16_t h) {
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/*
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* Extend the half-precision floating-point number to 32 bits and shift to the upper part of the 32-bit word:
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* +---+-----+------------+-------------------+
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* | S |EEEEE|MM MMMM MMMM|0000 0000 0000 0000|
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* +---+-----+------------+-------------------+
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* Bits 31 26-30 16-25 0-15
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*
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* S - sign bit, E - bits of the biased exponent, M - bits of the mantissa, 0 - zero bits.
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*/
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const uint32_t w = (uint32_t) h << 16;
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/*
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* Extract the sign of the input number into the high bit of the 32-bit word:
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*
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* +---+----------------------------------+
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* | S |0000000 00000000 00000000 00000000|
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* +---+----------------------------------+
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* Bits 31 0-31
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*/
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const uint32_t sign = w & UINT32_C(0x80000000);
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/*
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* Extract mantissa and biased exponent of the input number into the high bits of the 32-bit word:
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*
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* +-----+------------+---------------------+
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* |EEEEE|MM MMMM MMMM|0 0000 0000 0000 0000|
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* +-----+------------+---------------------+
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* Bits 27-31 17-26 0-16
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*/
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const uint32_t two_w = w + w;
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/*
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* Shift mantissa and exponent into bits 23-28 and bits 13-22 so they become mantissa and exponent
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* of a single-precision floating-point number:
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*
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* S|Exponent | Mantissa
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* +-+---+-----+------------+----------------+
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* |0|000|EEEEE|MM MMMM MMMM|0 0000 0000 0000|
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* +-+---+-----+------------+----------------+
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* Bits | 23-31 | 0-22
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*
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* Next, the exponent is adjusted for the difference in exponent bias between single-precision and half-precision
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* formats (0x7F - 0xF = 0x70). This operation never overflows or generates non-finite values, as the largest
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* half-precision exponent is 0x1F and after the adjustment is can not exceed 0x8F < 0xFE (largest single-precision
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* exponent for non-finite values).
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*
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* Note that this operation does not handle denormal inputs (where biased exponent == 0). However, they also do not
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* operate on denormal inputs, and do not produce denormal results.
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*/
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const uint32_t exp_offset = UINT32_C(0x70) << 23;
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const float normalized_value = fp32_from_bits((two_w >> 4) + exp_offset);
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/*
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* Convert denormalized half-precision inputs into single-precision results (always normalized).
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* Zero inputs are also handled here.
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*
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* In a denormalized number the biased exponent is zero, and mantissa has on-zero bits.
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* First, we shift mantissa into bits 0-9 of the 32-bit word.
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*
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* zeros | mantissa
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* +---------------------------+------------+
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* |0000 0000 0000 0000 0000 00|MM MMMM MMMM|
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* +---------------------------+------------+
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* Bits 10-31 0-9
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*
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* Now, remember that denormalized half-precision numbers are represented as:
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* FP16 = mantissa * 2**(-24).
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* The trick is to construct a normalized single-precision number with the same mantissa and thehalf-precision input
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* and with an exponent which would scale the corresponding mantissa bits to 2**(-24).
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* A normalized single-precision floating-point number is represented as:
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* FP32 = (1 + mantissa * 2**(-23)) * 2**(exponent - 127)
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* Therefore, when the biased exponent is 126, a unit change in the mantissa of the input denormalized half-precision
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* number causes a change of the constructud single-precision number by 2**(-24), i.e. the same ammount.
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*
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* The last step is to adjust the bias of the constructed single-precision number. When the input half-precision number
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* is zero, the constructed single-precision number has the value of
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* FP32 = 1 * 2**(126 - 127) = 2**(-1) = 0.5
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* Therefore, we need to subtract 0.5 from the constructed single-precision number to get the numerical equivalent of
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* the input half-precision number.
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*/
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const uint32_t magic_mask = UINT32_C(126) << 23;
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const float magic_bias = 0.5f;
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const float denormalized_value = fp32_from_bits((two_w >> 17) | magic_mask) - magic_bias;
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/*
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* - Choose either results of conversion of input as a normalized number, or as a denormalized number, depending on the
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* input exponent. The variable two_w contains input exponent in bits 27-31, therefore if its smaller than 2**27, the
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* input is either a denormal number, or zero.
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* - Combine the result of conversion of exponent and mantissa with the sign of the input number.
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*/
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const uint32_t denormalized_cutoff = UINT32_C(1) << 27;
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const uint32_t result = sign |
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(two_w < denormalized_cutoff ? fp32_to_bits(denormalized_value) : fp32_to_bits(normalized_value));
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return fp32_from_bits(result);
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}
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/*
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* Convert a 32-bit floating-point number in IEEE single-precision format to a 16-bit floating-point number in
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* ARM alternative half-precision format, in bit representation.
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*
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* @note The implementation relies on IEEE-like (no assumption about rounding mode and no operations on denormals)
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* floating-point operations and bitcasts between integer and floating-point variables.
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*/
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static inline uint16_t fp16_alt_from_fp32_value(float f) {
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const uint32_t w = fp32_to_bits(f);
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const uint32_t sign = w & UINT32_C(0x80000000);
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const uint32_t shl1_w = w + w;
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const uint32_t shl1_max_fp16_fp32 = UINT32_C(0x8FFFC000);
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const uint32_t shl1_base = shl1_w > shl1_max_fp16_fp32 ? shl1_max_fp16_fp32 : shl1_w;
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uint32_t shl1_bias = shl1_base & UINT32_C(0xFF000000);
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const uint32_t exp_difference = 23 - 10;
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const uint32_t shl1_bias_min = (127 - 1 - exp_difference) << 24;
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if (shl1_bias < shl1_bias_min) {
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shl1_bias = shl1_bias_min;
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}
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const float bias = fp32_from_bits((shl1_bias >> 1) + ((exp_difference + 2) << 23));
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const float base = fp32_from_bits((shl1_base >> 1) + (2 << 23)) + bias;
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const uint32_t exp_f = fp32_to_bits(base) >> 13;
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return (sign >> 16) | ((exp_f & UINT32_C(0x00007C00)) + (fp32_to_bits(base) & UINT32_C(0x00000FFF)));
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}
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#endif /* FP16_FP16_H */
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