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303 lines
7.6 KiB
303 lines
7.6 KiB
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <string.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <drivers/mmc.h>
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#include <lib/mmio.h>
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#include <imx_usdhc.h>
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static void imx_usdhc_initialize(void);
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static int imx_usdhc_send_cmd(struct mmc_cmd *cmd);
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static int imx_usdhc_set_ios(unsigned int clk, unsigned int width);
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static int imx_usdhc_prepare(int lba, uintptr_t buf, size_t size);
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static int imx_usdhc_read(int lba, uintptr_t buf, size_t size);
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static int imx_usdhc_write(int lba, uintptr_t buf, size_t size);
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static const struct mmc_ops imx_usdhc_ops = {
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.init = imx_usdhc_initialize,
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.send_cmd = imx_usdhc_send_cmd,
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.set_ios = imx_usdhc_set_ios,
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.prepare = imx_usdhc_prepare,
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.read = imx_usdhc_read,
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.write = imx_usdhc_write,
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};
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static imx_usdhc_params_t imx_usdhc_params;
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#define IMX7_MMC_SRC_CLK_RATE (200 * 1000 * 1000)
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static void imx_usdhc_set_clk(int clk)
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{
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int div = 1;
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int pre_div = 1;
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unsigned int sdhc_clk = IMX7_MMC_SRC_CLK_RATE;
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uintptr_t reg_base = imx_usdhc_params.reg_base;
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assert(clk > 0);
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while (sdhc_clk / (16 * pre_div) > clk && pre_div < 256)
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pre_div *= 2;
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while (sdhc_clk / div > clk && div < 16)
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div++;
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pre_div >>= 1;
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div -= 1;
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clk = (pre_div << 8) | (div << 4);
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mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN);
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mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk);
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udelay(10000);
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mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_PER_CLKEN | VENDSPEC_CARD_CLKEN);
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}
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static void imx_usdhc_initialize(void)
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{
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unsigned int timeout = 10000;
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uintptr_t reg_base = imx_usdhc_params.reg_base;
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assert((imx_usdhc_params.reg_base & MMC_BLOCK_MASK) == 0);
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/* reset the controller */
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mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTA);
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/* wait for reset done */
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while ((mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTA)) {
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if (!timeout)
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ERROR("IMX MMC reset timeout.\n");
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timeout--;
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}
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mmio_write_32(reg_base + MMCBOOT, 0);
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mmio_write_32(reg_base + MIXCTRL, 0);
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mmio_write_32(reg_base + CLKTUNECTRLSTS, 0);
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mmio_write_32(reg_base + VENDSPEC, VENDSPEC_INIT);
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mmio_write_32(reg_base + DLLCTRL, 0);
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mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_IPG_CLKEN | VENDSPEC_PER_CLKEN);
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/* Set the initial boot clock rate */
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imx_usdhc_set_clk(MMC_BOOT_CLK_RATE);
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udelay(100);
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/* Clear read/write ready status */
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mmio_clrbits32(reg_base + INTSTATEN, INTSTATEN_BRR | INTSTATEN_BWR);
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/* configure as little endian */
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mmio_write_32(reg_base + PROTCTRL, PROTCTRL_LE);
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/* Set timeout to the maximum value */
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mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_TIMEOUT_MASK,
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SYSCTRL_TIMEOUT(15));
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/* set wartermark level as 16 for safe for MMC */
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mmio_clrsetbits32(reg_base + WATERMARKLEV, WMKLV_MASK, 16 | (16 << 16));
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}
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#define FSL_CMD_RETRIES 1000
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static int imx_usdhc_send_cmd(struct mmc_cmd *cmd)
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{
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uintptr_t reg_base = imx_usdhc_params.reg_base;
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unsigned int xfertype = 0, mixctl = 0, multiple = 0, data = 0, err = 0;
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unsigned int state, flags = INTSTATEN_CC | INTSTATEN_CTOE;
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unsigned int cmd_retries = 0;
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assert(cmd);
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/* clear all irq status */
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mmio_write_32(reg_base + INTSTAT, 0xffffffff);
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/* Wait for the bus to be idle */
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do {
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state = mmio_read_32(reg_base + PSTATE);
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} while (state & (PSTATE_CDIHB | PSTATE_CIHB));
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while (mmio_read_32(reg_base + PSTATE) & PSTATE_DLA)
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;
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mmio_write_32(reg_base + INTSIGEN, 0);
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udelay(1000);
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switch (cmd->cmd_idx) {
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case MMC_CMD(12):
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xfertype |= XFERTYPE_CMDTYP_ABORT;
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break;
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case MMC_CMD(18):
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multiple = 1;
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/* fall thru for read op */
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case MMC_CMD(17):
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case MMC_CMD(8):
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mixctl |= MIXCTRL_DTDSEL;
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data = 1;
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break;
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case MMC_CMD(25):
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multiple = 1;
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/* fall thru for data op flag */
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case MMC_CMD(24):
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data = 1;
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break;
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default:
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break;
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}
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if (multiple) {
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mixctl |= MIXCTRL_MSBSEL;
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mixctl |= MIXCTRL_BCEN;
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}
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if (data) {
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xfertype |= XFERTYPE_DPSEL;
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mixctl |= MIXCTRL_DMAEN;
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}
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if (cmd->resp_type & MMC_RSP_48 && cmd->resp_type != MMC_RESPONSE_R2)
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xfertype |= XFERTYPE_RSPTYP_48;
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else if (cmd->resp_type & MMC_RSP_136)
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xfertype |= XFERTYPE_RSPTYP_136;
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else if (cmd->resp_type & MMC_RSP_BUSY)
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xfertype |= XFERTYPE_RSPTYP_48_BUSY;
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if (cmd->resp_type & MMC_RSP_CMD_IDX)
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xfertype |= XFERTYPE_CICEN;
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if (cmd->resp_type & MMC_RSP_CRC)
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xfertype |= XFERTYPE_CCCEN;
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xfertype |= XFERTYPE_CMD(cmd->cmd_idx);
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/* Send the command */
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mmio_write_32(reg_base + CMDARG, cmd->cmd_arg);
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mmio_clrsetbits32(reg_base + MIXCTRL, MIXCTRL_DATMASK, mixctl);
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mmio_write_32(reg_base + XFERTYPE, xfertype);
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/* Wait for the command done */
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do {
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state = mmio_read_32(reg_base + INTSTAT);
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if (cmd_retries)
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udelay(1);
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} while ((!(state & flags)) && ++cmd_retries < FSL_CMD_RETRIES);
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if ((state & (INTSTATEN_CTOE | CMD_ERR)) || cmd_retries == FSL_CMD_RETRIES) {
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if (cmd_retries == FSL_CMD_RETRIES)
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err = -ETIMEDOUT;
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else
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err = -EIO;
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ERROR("imx_usdhc mmc cmd %d state 0x%x errno=%d\n",
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cmd->cmd_idx, state, err);
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goto out;
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}
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/* Copy the response to the response buffer */
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if (cmd->resp_type & MMC_RSP_136) {
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unsigned int cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
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cmdrsp3 = mmio_read_32(reg_base + CMDRSP3);
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cmdrsp2 = mmio_read_32(reg_base + CMDRSP2);
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cmdrsp1 = mmio_read_32(reg_base + CMDRSP1);
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cmdrsp0 = mmio_read_32(reg_base + CMDRSP0);
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cmd->resp_data[3] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
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cmd->resp_data[2] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
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cmd->resp_data[1] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
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cmd->resp_data[0] = (cmdrsp0 << 8);
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} else {
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cmd->resp_data[0] = mmio_read_32(reg_base + CMDRSP0);
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}
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/* Wait until all of the blocks are transferred */
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if (data) {
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flags = DATA_COMPLETE;
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do {
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state = mmio_read_32(reg_base + INTSTAT);
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if (state & (INTSTATEN_DTOE | DATA_ERR)) {
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err = -EIO;
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ERROR("imx_usdhc mmc data state 0x%x\n", state);
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goto out;
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}
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} while ((state & flags) != flags);
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}
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out:
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/* Reset CMD and DATA on error */
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if (err) {
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mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTC);
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while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTC)
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;
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if (data) {
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mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTD);
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while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTD)
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;
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}
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}
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/* clear all irq status */
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mmio_write_32(reg_base + INTSTAT, 0xffffffff);
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return err;
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}
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static int imx_usdhc_set_ios(unsigned int clk, unsigned int width)
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{
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uintptr_t reg_base = imx_usdhc_params.reg_base;
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imx_usdhc_set_clk(clk);
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if (width == MMC_BUS_WIDTH_4)
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mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK,
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PROTCTRL_WIDTH_4);
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else if (width == MMC_BUS_WIDTH_8)
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mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK,
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PROTCTRL_WIDTH_8);
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return 0;
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}
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static int imx_usdhc_prepare(int lba, uintptr_t buf, size_t size)
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{
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uintptr_t reg_base = imx_usdhc_params.reg_base;
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mmio_write_32(reg_base + DSADDR, buf);
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mmio_write_32(reg_base + BLKATT,
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(size / MMC_BLOCK_SIZE) << 16 | MMC_BLOCK_SIZE);
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return 0;
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}
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static int imx_usdhc_read(int lba, uintptr_t buf, size_t size)
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{
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return 0;
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}
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static int imx_usdhc_write(int lba, uintptr_t buf, size_t size)
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{
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return 0;
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}
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void imx_usdhc_init(imx_usdhc_params_t *params,
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struct mmc_device_info *mmc_dev_info)
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{
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assert((params != 0) &&
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((params->reg_base & MMC_BLOCK_MASK) == 0) &&
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(params->clk_rate > 0) &&
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((params->bus_width == MMC_BUS_WIDTH_1) ||
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(params->bus_width == MMC_BUS_WIDTH_4) ||
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(params->bus_width == MMC_BUS_WIDTH_8)));
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memcpy(&imx_usdhc_params, params, sizeof(imx_usdhc_params_t));
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mmc_init(&imx_usdhc_ops, params->clk_rate, params->bus_width,
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params->flags, mmc_dev_info);
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}
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